# US 2019/0172783 A1 · Capacitance reduction in sea of lines beol metallization

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- Number: US 2019/0172783 A1
- Document ID: US20190172783A1
- Status: Published application
- Kind: A1
- Application number: 15/829,435
- Filed: 2017-12-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Benjamin D. Briggs; Lawrence A. Clevenger; Huai Huang; Christopher J. Penny; Michael Rizzolo; Hosadurga Shobha
- Web page: https://patentgrep.com/patent/US20190172783A1

## CPC

- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of interconnect lines including metal lines and neighboring dummy lines. The semiconductor interconnect structure further includes a dielectric layer arranged between the sea of lines.

## Claims

### Claim 1

A semiconductor interconnect structure, comprising:
a sea of interconnect lines including metal lines and neighboring dummy lines; and
a dielectric layer arranged between the sea of lines,
wherein the metal lines and the dummy lines are arranged in an array, and wherein the metal lines have a same height and a same width as the dummy lines, and wherein each of the metal lines is disposed in an alternating manner with respect to each of the dummy lines.

### Claim 2 (depends on 1)

The semiconductor interconnect structure of claim 1, wherein the metal lines and the dummy lines are initially formed of metal, and wherein airgaps replace the metal forming the dummy lines to reduce a parasitic capacitance resulting from the metal forming the dummy lines.

### Claim 3 (depends on 2)

The semiconductor interconnect structure of claim 2, wherein the metal lines and dummy lines are further formed to include a liner layer around peripheries of the dummy lines and the metal lines, and wherein the airgaps further replace the liner layer around the peripheries of the dummy lines.

### Claim 4 (depends on 2)

The semiconductor interconnect structure of claim 2, wherein the metal lines and dummy lines are further formed to include a barrier layer around the liner layer of the dummy lines and the metal lines, and wherein the airgaps further replace the barrier layer around the peripheries of the dummy lines.

### Claim 5 (depends on 2)

The semiconductor interconnect structure of claim 2, further comprising a dielectric filling in the airgaps.

### Claim 6 (depends on 2)

The semiconductor interconnect structure of claim 2, wherein a k value of the dielectric filling in the airgaps is lower than a k value of the dielectric layer arranged between the sea of lines.

### Claim 7 (depends on 2)

The semiconductor interconnect structure of claim 2, further comprising a non-conformal dielectric cap formed over the semiconductor interconnect structure to seal in the airgaps.

### Claim 8 (depends on 1)

The semiconductor interconnect structure of claim 1, wherein the semiconductor interconnect structure is disposed in a Back End Of Line portion of a semiconductor device having one or more active components.

### Claim at position 9

9-10. (canceled)

### Claim 11 (depends on 1)

The semiconductor interconnect structure of claim 1, wherein the metal lines and the dummy lines are embedded in and coplanar with the dielectric layer.

### Claim at position 11

12-20. (canceled)

### Claim 21 (depends on 1)

The semiconductor interconnect structure of claim 1, wherein a single dummy line is inter-disposed between one or more pairs of the metal lines.