# US 2019/0172782 A1 · Packaging substrate for semiconductor devices, corresponding device and method

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- Number: US 2019/0172782 A1
- Document ID: US20190172782A1
- Status: Published application
- Kind: A1
- Application number: 16/269,300
- Filed: 2019-02-06
- Published: 2019-06-06
- Earliest claimed: 2015-11-10
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Federico Giovanni ZIGLIOLI
- Web page: https://patentgrep.com/patent/US20190172782A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H05K 1/0287: {having an universal lay-out, e.g. pad or land grid patterns or mesh patterns}
- H05K 1/0289: {having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes}
- H05K 1/0295: {adapted for choosing between different types or different locations of mounted components}
- H05K 1/112: {directly combined with via connections}
- H05K 3/107: {by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence)}
- H05K 3/205: {using a pattern electroplated or electroformed on a metallic carrier}
- H05K 3/4015: {using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres}
- H05K 3/4046: {using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire}
- H10W 70/042: {Etching}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 72/50: Bond wires
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H05K 2201/09409: Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
- H05K 2201/09945: Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
- H05K 2201/10378: Interposers
- H05K 2203/025: Abrading, e.g. grinding or sand blasting
- H05K 2203/0338: Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
- H05K 2203/0361: Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
- H05K 2203/0369: Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
- H05K 2203/1189: Pressing leads, bumps or a die through an insulating layer
- H05K 2203/143: Treating holes before another process, e.g. coating holes before coating the substrate
- H05K 2203/1461: Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K 2203/1476: Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
- H05K 2203/308: Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

## Claims

### Claim 1

A method, comprising:
etching a first surface of an electrically conductive laminar carrier to produce first raised portions corresponding to locations of first lands and produce a recessed surface,
further etching said recessed surface of said electrically conductive laminar carrier to produce indented portions between second raised portions corresponding to locations of second lands,
molding onto said first surface of said electrically conductive laminar carrier an electrically insulating molding material that penetrates into said indented portions and covers said recessed surface of said laminar carrier at said second raised portions, and
removing a portion of said electrically conductive laminar carrier at a second surface opposite the first surface to expose the molding compound which penetrated into said indented portions.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing comprises reducing a thickness of the electrically conductive laminar carrier from the second surface.

### Claim 3 (depends on 1)

The method of claim 1, wherein portions of said electrically conductive laminar carrier which remain after the step of removing define the first lands having a first thickness and the second lands having a second thickness less than the first thickness.

### Claim 4 (depends on 1)

The method of claim 1, wherein removing produces the first and second lands as structures which are insulated from each other by the molding compound which penetrated into said indented portions and covered said recessed surface of said laminar carrier.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming metal tracks on a top surface resulting from the step of removing, said metal tracks electrically interconnecting at least one second land to another second land.

### Claim 6 (depends on 5)

The method of claim 5, wherein forming the metal tracks comprises printing lines made of conductive material on the top surface.

### Claim 7 (depends on 6)

The method of claim 6, wherein printing comprises ink jet printing.

### Claim 8 (depends on 6)

The method of claim 6, wherein the lines have a width in a range of 50-100 microns and a thickness in a range of 10-20 microns.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming metal tracks on a top surface resulting from the step of removing, said metal tracks electrically interconnecting at least one first land to at least one second land.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the metal tracks comprises printing lines made of conductive material on the top surface.

### Claim 11 (depends on 10)

The method of claim 10, wherein printing comprises ink jet printing.

### Claim 12 (depends on 10)

The method of claim 10, wherein the lines have a width in a range of 50-100 microns and a thickness in a range of 10-20 microns.

### Claim 13

A method, comprising:
growing first and second electrically conductive formations on a first surface of a sacrificial carrier layer, wherein said first electrically conductive formations correspond to locations of first lands, and wherein said second electrically conductive formations correspond to locations of seconds lands,
depositing an insulating material on said first surface of said sacrificial carrier layer to penetrate into indented portions between said second electrically conductive formations and cover said second electrically conductive formations while leaving said first electrically conductive formations uncovered, and
removing the sacrificial carrier layer to produce a substrate including said first and second lands insulated from each other by the insulating material and having exposed surfaces of the both the first and second lands at a top surface of the substrate and exposed surfaces of only the first lands at a second surface of the substrate opposite the first surface.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first lands have a first thickness and the second lands have a second thickness less than the first thickness.

### Claim 15 (depends on 13)

The method of claim 13, further comprising forming metal tracks on the top surface, said metal tracks electrically interconnecting at least one second land to another second land.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the metal tracks comprises printing lines made of conductive material on the top surface.

### Claim 17 (depends on 16)

The method of claim 16, wherein printing comprises ink jet printing.

### Claim 18 (depends on 16)

The method of claim 16, wherein the lines have a width in a range of 50-100 microns and a thickness in a range of 10-20 microns.

### Claim 19 (depends on 13)

The method of claim 13, further comprising forming metal tracks on a top surface, said metal tracks electrically interconnecting at least one first land to at least one second land.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the metal tracks comprises printing lines made of conductive material on the top surface.

### Claim 21 (depends on 20)

The method of claim 20, wherein printing comprises ink jet printing.

### Claim 22 (depends on 20)

The method of claim 20, wherein the lines have a width in a range of 50-100 microns and a thickness in a range of 10-20 microns.

### Claim 23 (depends on 13)

The method of claim 13, wherein depositing the insulating material comprises applying a mask material on said first surface of said sacrificial carrier layer to penetrate into indented portions between said second electrically conductive formations and cover said second electrically conductive formations while leaving said first electrically conductive formations uncovered, the method further comprising:
further growing electrically conductive material onto said uncovered first electrically conductive formations, and
molding onto said first surface of said sacrificial carrier layer an electrically insulating molding material that fills space between the further grown electrically conductive material.