# US 2019/0172774 A1 · Recessed lead leadframe packages > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172774 A1 - Document ID: US20190172774A1 - Status: Published application - Kind: A1 - Application number: 16/269,914 - Filed: 2019-02-07 - Published: 2019-06-06 - Earliest claimed: 2015-07-16 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Francois RICODEAU - Web page: https://patentgrep.com/patent/US20190172774A1 ## CPC - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 70/417: {Bonding materials between chips and die pads} - H10W 70/421: {Shapes or dispositions} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip. The at least one of the plurality of leads that is not configured to mechanically coupled at the surface of the semiconductor chip be configured to electrically couple with the semiconductor chip ## Claims ### Claim 1 A chip-on-lead package comprising: a leadframe coupled to a semiconductor chip, the leadframe comprising a plurality of leads extending inwardly into an opening in the leadframe surrounded by the plurality of leads; wherein at least one of the plurality of leads comprises a thinned portion adjacent to the semiconductor chip and is an at least one thinned lead; and wherein the plurality of leads, except for the at least one thinned lead, mechanically couple to the semiconductor chip through a die bonding material. ### Claim 2 (depends on 1) The package of claim 1, wherein the at least one thinned lead is configured to carry up to 200 volts. ### Claim 3 (depends on 1) The package of claim 1, wherein the thinned portion of the at least one thinned lead is one of half etched and fully etched. ### Claim 4 (depends on 1) The package of claim 1, wherein the plurality of leads is configured to couple with an electronic circuit board at a surface of each of the plurality of leads opposite the surface of the semiconductor chip. ### Claim 5 (depends on 1) The package of claim 1, wherein the at least one thinned lead does not extend inwardly into the opening as far as the other leads of the plurality of leads. ### Claim 6 (depends on 1) The package of claim 1, wherein the plurality of leads is configured to mechanically support the semiconductor chip through coupling at the surface of the semiconductor chip through a die bonding material. ### Claim 7 (depends on 1) The package of claim 1, wherein a perimeter of the surface of each of the plurality of leads opposite the surface of the semiconductor chip except for the at least one thinned lead is smaller than a perimeter of a surface of each of the plurality of leads configured to be coupled at the surface of the semiconductor chip. ### Claim 8 (depends on 7) The package of claim 7, wherein the surface of each of the plurality of leads except for the at least one thinned lead opposite the surface of the semiconductor chip is half etched. ### Claim 9 A chip-on-lead package comprising: a leadframe coupled to a semiconductor chip, the leadframe comprising a plurality of leads extending inwardly into an opening in the leadframe surrounded by the plurality of leads; wherein at least one lead electrically couples with a high voltage connector of the semiconductor chip; and wherein the plurality of leads, except for the at least one lead, mechanically couple to the semiconductor chip through a die bonding material. ### Claim 10 (depends on 9) The package of claim 9, wherein the at least one lead is configured to carry up to 200 volts. ### Claim 11 (depends on 9) The package of claim 9, wherein the at least one thinned lead is one of half etched and fully etched. ### Claim 12 (depends on 9) The package of claim 9, wherein the plurality of leads is configured to couple with an electronic circuit board at a surface of each of the plurality of leads opposite the surface of the semiconductor chip. ### Claim 13 (depends on 9) The package of claim 9, wherein the at least one lead does not extend inwardly into the opening as far as the other leads of the plurality of leads. ### Claim 14 (depends on 9) The package of claim 9, wherein the plurality of leads is configured to mechanically support the semiconductor chip through coupling at the surface of the semiconductor chip through a die bonding material. ### Claim 15 (depends on 9) The package of claim 9, wherein a perimeter of the surface of each of the plurality of leads opposite the surface of the semiconductor chip except for the at least one lead is smaller than a perimeter of a surface of each of the plurality of leads configured to be coupled at the surface of the semiconductor chip. ### Claim 16 (depends on 15) The package of claim 15, wherein the surface of each of the plurality of leads except for the at least one lead opposite the surface of the semiconductor chip is half etched. ### Claim 17 A chip-on-lead package comprising: a leadframe coupled to a semiconductor chip, the leadframe comprising a plurality of leads extending inwardly into an opening in the leadframe surrounded by the plurality of leads; wherein at least one of the plurality of leads comprises a thinned portion and is an at least one thinned lead. ### Claim 18 (depends on 17) The package of claim 17, wherein the at least one thinned lead is configured to carry up to 200 volts. ### Claim 19 (depends on 17) The package of claim 17, wherein the thinned portion of the at least one thinned lead is one of half etched and fully etched. ### Claim 20 (depends on 17) The package of claim 17, wherein the plurality of leads is configured to couple with an electronic circuit board at a surface of each of the plurality of leads opposite a surface of the semiconductor chip.