# US 2019/0172773 A1 · Semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172773 A1 - Document ID: US20190172773A1 - Status: Published application - Kind: A1 - Application number: 16/210,135 - Filed: 2018-12-05 - Published: 2019-06-06 - Earliest claimed: 2017-12-06 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Atsushi KUROKAWA; Masayuki AOIKE; Takayuki TSUTSUI - Web page: https://patentgrep.com/patent/US20190172773A1 ## CPC - H10W 72/50: Bond wires - H10W 20/43: Layouts of interconnections - H10W 20/4421: {the principal metal being copper} - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 74/476: {Organic materials comprising silicon} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/073: {of die-attach connectors} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/874: {On different surfaces} - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/9413: {on encapsulations} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the wiring. A cavity entirely overlapping with the wiring as viewed from above is formed in the insulating film. A metal member electrically connected to the wiring via the cavity is disposed on the insulating film. The centroid of the cavity is displaced from that of the operating region of the corresponding unit transistor in the first direction. When the cavity having a centroid the closest to the operating region of a unit transistor is defined as the closest proximity cavity, the amount of deviation of the centroid of the closest proximity cavity from that of the operating region of the corresponding unit transistor in the first direction becomes greater from the center to the ends of the arrangement direction of the unit transistors. ## Claims ### Claim 1 A semiconductor apparatus comprising: a substrate; a plurality of unit transistors provided on the substrate, each of the plurality of unit transistors including an operating region through which an operating current flows; a first wiring disposed above the operating regions of the plurality of unit transistors to serve as a path for the operating current to flow through the plurality of unit transistors; an insulating film disposed on the first wiring and including at least one cavity, an entirety of the at least one cavity overlapping with the first wiring as viewed from above; and a metal member disposed on the insulating film and electrically connected to the first wiring via the at least one cavity, wherein the plurality of unit transistors are disposed on the substrate side by side in a first direction, a centroid of the at least one cavity is displaced from a centroid of the operating region of each of the plurality of unit transistors in the first direction, as viewed from above, and for each of the unit transistors, when, among the at least one cavity, a cavity having a centroid positioned most closely to the centroid of the operating region of a given unit transistor is defined as a closest proximity cavity for the given unit transistor, an amount of deviation of the centroid of the closest proximity cavity from the centroid of the operating region of the corresponding unit transistor in the first direction becomes greater from a center to an end of an arrangement direction of the plurality of unit transistors. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the at least one cavity is disposed between the centroids of the operating regions of two of the unit transistors located at both ends in the first direction, and no cavity is disposed outside the centroids of the operating regions of the two unit transistors. ### Claim 3 (depends on 1) The semiconductor apparatus according to claim 1, wherein at least two of the at least one cavity are disposed at different positions in a direction perpendicular to the first direction. ### Claim 4 (depends on 1) The semiconductor apparatus according to claim 1, wherein the centroid of the operating region of each of the plurality of unit transistors is displaced from a centroid of the metal member in a direction perpendicular to the first direction, as viewed from above. ### Claim 5 (depends on 1) The semiconductor apparatus according to claim 1, wherein the operating region of each of the plurality of unit transistors has a planar configuration elongated in a direction perpendicular to the first direction. ### Claim 6 (depends on 1) The semiconductor apparatus according to claim 1, wherein the metal member forms a pillar bump including a metal post comprising copper as a main constituent. ### Claim 7 (depends on 1) The semiconductor apparatus according to claim 1, wherein: the metal member forms a second wiring disposed above the substrate; the semiconductor apparatus further comprises an external connection terminal disposed on the second wiring; and the metal member is electrically connected to the external connection terminal. ### Claim 8 (depends on 1) The semiconductor apparatus according to claim 1, wherein the insulating film includes at least one of silicon oxide, silicon nitride, and a resin as a material. ### Claim 9 (depends on 1) The semiconductor apparatus according to claim 1, wherein: each of the plurality of unit transistors is a bipolar transistor including a collector layer, a base layer, and an emitter layer provided on the substrate; and the operating region is a region where the operating current flows in a thickness direction of each of the plurality of unit transistors. ### Claim 10 (depends on 9) The semiconductor apparatus according to claim 9, wherein: the collector layer, the base layer, and the emitter layer of each of the plurality of unit transistors are sequentially stacked on the substrate; the emitter layer is electrically connected to the first wiring; and an interface between the base layer and the emitter layer is a heterojunction. ### Claim 11 (depends on 10) The semiconductor apparatus according to claim 10, wherein the substrate comprises GaAs and the emitter layer comprises InGaP. ### Claim 12 (depends on 10) The semiconductor apparatus according to claim 10, wherein each of the plurality of unit transistors is a heterojunction bipolar transistor including the base layer comprising SiGe. ### Claim 13 (depends on 1) The semiconductor apparatus according to claim 1, wherein: each of the plurality of unit transistors is a field-effect transistor including a source, a drain, and a gate provided on the substrate; and the operating region is a region where the operating current flows in an in-plane direction on a surface of the substrate. ### Claim 14 A semiconductor apparatus comprising: a substrate; a plurality of unit transistors provided on the substrate, each of the plurality of unit transistors including an operating region through which an operating current flows; a wiring disposed above the operating regions of the plurality of unit transistors to serve as a path for the operating current to flow through the plurality of unit transistors; an insulating film disposed on the wiring and including at least one cavity, an entirety of the at least one cavity overlapping with the wiring as viewed from above; and a metal member disposed on the insulating film and electrically connected to the wiring via the at least one cavity, wherein the plurality of unit transistors are disposed on the substrate side by side in a first direction, a centroid of the at least one cavity is displaced from a centroid of the operating region of each of the plurality of unit transistors in the first direction, as viewed from above, and for each of the unit transistors, when, among the at least one cavity, a cavity having a centroid positioned most closely to the centroid of the operating region of a given unit transistor is defined as a closest proximity cavity for the given unit transistor, an amount of deviation of the centroid of the closest proximity cavity in the first direction from the centroid of the operating region of the unit transistor positioned at one end in the first direction is smaller than an amount of deviation of the centroid of the closest proximity cavity in the first direction from the centroid of the operating region of the unit transistor positioned at the other end in the first direction. ### Claim 15 (depends on 14) The semiconductor apparatus according to claim 14, wherein the amount of deviation of the centroid of the closest proximity cavity from the centroid of the operating region of the corresponding unit transistor in the first direction becomes greater from one end to the other end in the first direction. ### Claim 16 A semiconductor apparatus comprising: a substrate; a plurality of unit transistors provided on the substrate, each of the plurality of unit transistors including at least one operating region through which an operating current flows; a wiring disposed above the operating regions of the plurality of unit transistors to serve as a path for the operating current to flow through the plurality of unit transistors; an insulating film disposed on the wiring and including at least one cavity, an entirety of the at least one cavity overlapping with the wiring as viewed from above; and a metal member disposed on the insulating film and electrically connected to the wiring via the at least one cavity, wherein the plurality of unit transistors are disposed on the substrate side by side in a first direction, as viewed from above, when the smallest rectangle containing the at least one operating region of each of the plurality of unit transistors therein is defined as an effective operating region, and, assuming that a line parallel with a second direction perpendicular to the first direction and passing through a midpoint of a segment between a centroid of a given effective operating region and a centroid of an adjacent effective operating region is set as an imaginary line, when each of a plurality of regions sandwiched between the imaginary lines is defined as a range influenced by the effective operating region positioned within the range, an area of an overlapping region where the range and the cavity overlap with each other differs among the effective operating regions, and areas of the overlapping regions corresponding to the effective operating regions positioned at both ends in the first direction are smaller than areas of the overlapping regions corresponding to the effective operating regions other than the effective operating regions positioned at both ends in the first direction. ### Claim 17 (depends on 2) The semiconductor apparatus according to claim 2, wherein at least two of the at least one cavity are disposed at different positions in a direction perpendicular to the first direction. ### Claim 18 (depends on 2) The semiconductor apparatus according to claim 2, wherein the centroid of the operating region of each of the plurality of unit transistors is displaced from a centroid of the metal member in a direction perpendicular to the first direction, as viewed from above. ### Claim 19 (depends on 3) The semiconductor apparatus according to claim 3, wherein the centroid of the operating region of each of the plurality of unit transistors is displaced from a centroid of the metal member in a direction perpendicular to the first direction, as viewed from above. ### Claim 20 (depends on 2) The semiconductor apparatus according to claim 2, wherein the operating region of each of the plurality of unit transistors has a planar configuration elongated in a direction perpendicular to the first direction.