# US 2019/0172769 A1 · Semiconductor die with improved ruggedness

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- Number: US 2019/0172769 A1
- Document ID: US20190172769A1
- Status: Published application
- Kind: A1
- Application number: 15/828,539
- Filed: 2017-12-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Cree, Inc.
- Applicants: Cree, Inc.
- Inventors: Chris Hardiman; Kyoung-Keun Lee; Fabian Radulescu; Daniel Namishia; Scott Thomas Sheppard
- Web page: https://patentgrep.com/patent/US20190172769A1

## CPC

- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10D 62/102: {Constructional design considerations for preventing surface leakage or controlling electric field concentration}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/147: {the encapsulations being multilayered}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 72/019: {of bond pads}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

## Claims

### Claim 1

A semiconductor die comprising:
a substrate, the substrate having boundaries defined by a substrate termination edge;
a first passivation layer over the substrate, the first passivation layer terminating at a first passivation termination edge that is inset from the substrate termination edge by a first distance; and
a second passivation layer over the first passivation layer and the substrate, the second passivation layer terminating at a second passivation termination edge that is inset from the substrate termination edge by a second distance, wherein the second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer and the second passivation layer is directly coupled to the first passivation termination edge.

### Claim 2 (depends on 1)

The semiconductor die of claim 1 further comprising a third passivation layer over the second passivation layer and the substrate, the third passivation layer terminating at a third passivation termination edge that is inset from the substrate termination edge by a third distance, wherein the third distance is less than the second distance such that the third passivation layer overlaps the second passivation layer.

### Claim 3 (depends on 2)

The semiconductor die of claim 2 wherein the substrate comprises:
an active area in which one or more active devices are provided; and
a barrier region surrounding the active area and configured to electrically isolate the active area from the substrate termination edge, wherein:
the barrier region terminates at a barrier region termination edge that is inset from the substrate termination edge by a fourth distance, wherein the fourth distance is greater than the third distance; and
a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.

### Claim 4 (depends on 3)

The semiconductor die of claim 3 wherein the region forming the charge redistribution path is implanted with dopants to increase the conductivity thereof.

### Claim 5 (depends on 3)

The semiconductor die of claim 3 wherein the charge redistribution path is coupled to a fixed potential.

### Claim 6 (depends on 3)

The semiconductor die of claim 3 wherein the fourth distance is greater than the second distance.

### Claim 7 (depends on 2)

The semiconductor die of claim 2 further comprising a charge redistribution path, the charge redistribution path comprising a metal layer under the second passivation layer between the first passivation termination edge and the second passivation termination edge.

### Claim 8 (depends on 7)

The semiconductor die of claim 7 wherein the charge redistribution path is coupled to a fixed potential.

### Claim 9 (depends on 1)

The semiconductor die of claim 1 wherein the substrate comprises:
an active area in which one or more active devices are provided; and
a barrier region surrounding the active area and configured to electrically isolate the active area from the substrate termination edge, wherein:
the barrier region terminates at a barrier region termination edge that is inset from the substrate termination edge by a third distance, wherein the third distance is greater than the second distance; and
a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.

### Claim 10 (depends on 9)

The semiconductor die of claim 9 wherein the region forming the charge redistribution path is implanted with dopants to increase the conductivity thereof.

### Claim 11 (depends on 9)

The semiconductor die of claim 9 wherein the charge redistribution path is coupled to a fixed potential.

### Claim 12 (depends on 1)

The semiconductor die of claim 1 further comprising a charge redistribution path, the charge redistribution path comprising a metal layer under the second passivation layer between the first passivation termination edge and the second passivation termination edge.

### Claim 13 (depends on 12)

The semiconductor die of claim 12 wherein the charge redistribution path is coupled to a fixed potential.

### Claim 14

A method for manufacturing a semiconductor die comprising:
providing a substrate, the substrate having boundaries defined by a substrate termination edge;
providing a first passivation layer over the substrate such that the first passivation layer terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance; and
providing a second passivation layer over the first passivation layer and the substrate such that the second passivation layer terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance, wherein the second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer and the second passivation layer is directly coupled to the first passivation termination edge.

### Claim 15 (depends on 14)

The method of claim 14 further comprising providing a third passivation layer over the second passivation layer and the substrate, the third passivation layer terminating at a third passivation termination edge that is inset from the substrate termination edge by a third distance, wherein the third distance is less than the second distance such that the third passivation layer overlaps the second passivation layer.

### Claim 16 (depends on 15)

The method of claim 15 further comprising providing a barrier region in the substrate, wherein the barrier region:
surrounds an active region in which one or more active devices are provided;
electrically isolates the active region from the substrate termination edge; and
terminates at a barrier region termination edge that is inset from the substrate termination edge by a fourth distance that is greater than the third distance such that a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.

### Claim 17 (depends on 16)

The method of claim 16 wherein the fourth distance is greater than the second distance.

### Claim 18 (depends on 15)

The method of claim 15 further comprising providing a charge redistribution path as a metal layer under the second passivation layer between the first passivation termination edge and the second passivation termination edge.

### Claim 19 (depends on 16)

The method of claim 16 further comprising coupling the charge redistribution path to a fixed potential.

### Claim 20 (depends on 14)

The method of claim 14 further comprising providing a barrier region in the substrate, wherein the barrier region:
surrounds an active region in which one or more active devices are provided;
electrically isolates the active region from the substrate termination edge; and
terminates at a barrier region termination edge that is inset from the substrate termination edge by a fourth distance that is greater than the third distance such that a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.

### Claim 21 (depends on 14)

The method of claim 14 further comprising providing a charge redistribution path as a metal layer under the second passivation layer between the first passivation termination edge and the second passivation termination edge.

### Claim 22 (depends on 21)

The method of claim 21 further comprising coupling the charge redistribution path to a fixed potential.