# US 2019/0172756 A1 · Hybrid high-voltage low-voltage finfet device

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- Number: US 2019/0172756 A1
- Document ID: US20190172756A1
- Status: Published application
- Kind: A1
- Application number: 16/177,715
- Filed: 2018-11-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Microsemi SoC Corporation
- Applicants: Microsemi SoC Corp.
- Inventors: John McCollum; Fethi Dhaoui; Pavan Singaraju
- Web page: https://patentgrep.com/patent/US20190172756A1

## CPC

- H10D 86/011: {comprising FinFETs}
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 34/00: Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

## Claims

### Claim 1

An integrated circuit comprising:
a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness; and
a plurality of hybrid FinFET transistors each having the channel length l and the channel width w, the hybrid FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 wherein:
the plurality of low-voltage FinFET transistors are n-channel FinFET transistors; and
the plurality of hybrid FinFET transistors are n-channel FinFET transistors.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 wherein:
the plurality of low-voltage FinFET transistors are p-channel FinFET transistors; and
the plurality of hybrid FinFET transistors are p-channel FinFET transistors.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 wherein:
the plurality of low-voltage FinFET transistors include both n-channel FinFET transistors and p-channel FinFET transistors; and
the plurality of hybrid FinFET transistors include both n-channel FinFET transistors an p-channel FinFET transistors.

### Claim 5

A method for fabricating gate dielectric regions for both low-voltage FinFET transistors and hybrid FinFET transistors, the method comprising:
forming a first layer of first dielectric material over fin structures in both low-voltage FinFET transistors and hybrid FinFET transistors;
applying a gate masking layer over the first layer of dielectric material for the hybrid FinFET transistors;
removing the first layer of dielectric material from the fin structures of the low-voltage FinFET transistors;
removing the hybrid gate masking layer;
forming a second layer of the first dielectric material over the fin structures in both the low-voltage FinFET transistors and hybrid FinFET transistors; and
forming a layer of a second dielectric layer over the fin structures of all low-voltage and hybrid FinFET transistors.

### Claim 6 (depends on 5)

The method of claim 5 wherein:
the first dielectric material is SiO2; and
the second dielectric material is HfO2.

### Claim 7

A method for implanting threshold channel implants for both low-voltage FinFET transistors and hybrid FinFET transistors, the method comprising:
performing a low-voltage threshold implant in the channel regions of both the low-voltage FinFET transistors and the hybrid FinFET transistors;
applying an implant masking layer covering the channel regions of the low-voltage FinFET transistors;
performing a hybrid channel threshold implant in the channel regions of the hybrid FinFET transistors; and
removing the voltage implant masking layer.

### Claim 8 (depends on 7)

The method of claim 7 wherein:
the low-voltage FinFET transistors and the hybrid FinFET transistors are re-channel transistors; and
performing the low-voltage and the hybrid channel threshold implants comprises implanting arsenic.

### Claim 9 (depends on 7)

The method of claim 7 wherein:
the low-voltage FinFET transistors and the hybrid FinFET transistors are p-channel transistors; and
performing the low-voltage and the hybrid channel threshold implants comprises implanting boron.

### Claim 10 (depends on 7)

The method of claim 7 wherein:
performing the low-voltage threshold implant in the channel regions of both the low-voltage FinFET transistors and the hybrid FinFET transistors comprises implanting to a level of about 3e18 atoms/cm3; and
performing the hybrid channel threshold implant in the channel regions of the hybrid FinFET transistors comprises implanting to a total level of about 5e18 atoms/cm3.

### Claim 11

A method for implanting threshold channel implants for both low-voltage FinFET transistors and hybrid FinFET transistors, the method comprising:
performing a low-voltage threshold implant in the channel regions of both the low-voltage n-channel FinFET transistors and the hybrid n-channel FinFET transistors;
applying an n-channel implant masking layer covering the channel regions of the low-voltage n-channel FinFET transistors;
performing a hybrid channel threshold implant in the channel regions of the hybrid n-channel FinFET transistors;
removing the n-channel implant masking layer;
performing a low-voltage threshold implant in the channel regions of both the low-voltage p-channel FinFET transistors and the hybrid p-channel FinFET transistors;
applying a p-channel implant masking layer covering the channel regions of the low-voltage p-channel FinFET transistors;
performing a hybrid channel threshold implant in the channel regions of the hybrid p-channel FinFET transistors; and
removing the p-channel implant masking layer.