# US 2019/0172755 A1 · Method for incorporating multiple channel materials in a complimentary field effective transistor (cfet) device

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- Number: US 2019/0172755 A1
- Document ID: US20190172755A1
- Status: Published application
- Kind: A1
- Application number: 16/204,606
- Filed: 2018-11-29
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Jeffrey SMITH; Subhadeep KAL
- Web page: https://patentgrep.com/patent/US20190172755A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 50/242: {of Group IV materials}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
providing a substrate having a base fin structure thereon, the base fin structure comprising:
a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion comprising first channel material,
a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion comprising second channel material, and
a sacrificial portion separating the first stack portion from the second stack portion provided between upper and lower portions of second sacrificial material such that the first channel material, second channel material and sacrificial material are exposed at a side of the base fin structure, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other;
exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material relative to the other two of the first channel material, the second channel material and the sacrificial material; and
forming first and second GAA gate structures around said first channel material and said second channel material respectively.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first channel material is Si, said second channel material is SiGe and said sacrificial material is doped Si.

### Claim 3 (depends on 2)

The method of claim 2, wherein said first channel material provides an NMOS channel and the second channel material provides a PMOS channel.

### Claim 4 (depends on 1)

The method of claim 1, wherein said exposing comprises selectively etching the first channel material in the width direction relative to the second channel material and the sacrificial material to form a vertically oriented first channel portion.

### Claim 5 (depends on 4)

The method of claim 4, wherein said first channel portion is a single layer of said first channel material and said second channel portion is a single layer of said second channel material, the layer of first channel material being thicker than the layer of second channel material along said height direction.

### Claim 6 (depends on 4)

The method of claim 4, wherein said first channel portion is a single layer of said first channel material and said second channel portion comprises a plurality of layers of said second channel material separated from each other by a layer of said sacrificial material in the height direction, the single layer of first channel material being thicker than any layer of the second channel material along said height direction.

### Claim 7 (depends on 1)

The method of claim 1, wherein said first channel portion comprises a plurality of layers of said first channel material separated from each other by a layer of said sacrificial material in the height direction, and said second channel portion comprises a plurality of layers of said second channel material separated from each other by a layer of said sacrificial material in the height direction.

### Claim 8 (depends on 1)

The method of claim 1, further comprising cutting said fin structure along said length to form a plurality of separate fin structures each having a cut end which exposes ends of the first channel material, the second channel material and the sacrificial material.

### Claim 9 (depends on 8)

The method of claim 8, wherein said exposing comprises exposing said cut end to the isotropic etch process to selectively etch the sacrificial material along the length direction such that the sacrificial material forms a recess relative to the first channel material and the second channel material.

### Claim 10 (depends on 8)

The method of claim 8, further comprising depositing a gate spacer dielectric material in the recess.

### Claim 11 (depends on 1)

The method of claim 1, wherein said exposing comprises selectively etching away all of the sacrificial material relative to the first channel material and the second channel material such that the first and second channel materials are released from the fin structure.

### Claim 12 (depends on 1)

The method of claim 1, wherein said forming gate structures comprises:
forming a first gate structure surrounding the first channel portion, and
forming a second gate structure surrounding the second channel portion.

### Claim 13 (depends on 12)

The method of claim 12, wherein said forming a first gate structure comprises:
forming an NMOS gate structure around the first channel portion, and
forming a PMOS gate structure around the second channel portion.

### Claim 14 (depends on 13)

The method of claim 13, further comprising electrically connecting the NMOS gate structure to the PMOS gate structure as complementary complementary transistors.

### Claim 15

A semiconductor device comprising:
a substrate having a planar surface;
a first FET provided on said substrate and having a first channel structure;
a second FET vertically stacked on said first FET along a height direction perpendicular to a planar surface, the second FET having a second channel structure;
a first gate structure provided all around said first channel structure; and
a second gate structure provided all around said second channel structure, wherein said first channel is vertically oriented and said second channel is horizontally oriented.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein said first channel structure is a single vertically oriented channel.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein said second channel structure comprises a plurality of stacked horizontally oriented channels.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein said first channel is an nFET channel and said second channel is a pFET channel.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein said first channel is a pFET channel and said second channel is an nFET channel.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein said first channel structure is formed of Si and said second channel structure is formed of SiGe.