# US 2019/0172736 A1 · Apparatus and method for securing components of an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172736 A1 - Document ID: US20190172736A1 - Status: Published application - Kind: A1 - Application number: 16/267,644 - Filed: 2019-02-05 - Published: 2019-06-06 - Earliest claimed: 2017-08-24 - Assignees: Cerebras Systems Inc. - Applicants: Cerebras Systems Inc. - Inventors: Jean-Philippe Fricker; Frank Jun; Paul Kennedy - Web page: https://patentgrep.com/patent/US20190172736A1 ## CPC - H10P 72/0438: {Apparatus for making assemblies not otherwise provided for, e.g. package constructions} - B32B 37/10: characterised by the pressing technique, e.g. using action of vacuum or fluid pressure - H01R 43/007: {for elastomeric connecting elements} - H10W 72/00: Interconnections or connectors in packages - H10W 72/0198: {batch processes} - H10W 72/0711: {Apparatus therefor} - H10W 90/00: Package configurations - H01R 12/52: connecting to other rigid printed circuits or like structures - H01R 13/2414: {conductive elastomers} - H10W 70/63: Vias, e.g. via plugs - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/07332: {Compression bonding, e.g. thermocompression bonding} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/351: {Materials of die-attach connectors} - H10W 72/354: {comprising polymers} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - B32B: LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements. ## Claims ### Claim 1 A method of securing an integrated circuit assembly, the method comprising: arranging each of a plurality of securing elements within one of a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; fastening each of the plurality of securing elements while the plurality of layer components of the integrated circuit assembly are in a compressed state based on a mechanical compression load; and releasing the plurality of layer components of the integrated circuit assembly from the compressed state to an uncompressed state based on the fastening of the plurality of securing elements. ### Claim 2 (depends on 1) The method according to claim 1, wherein at least one layer component of the integrated circuit assembly comprises a semiconductor substrate having: a plurality of die formed with the semiconductor substrate; a circuit layer formed at each of the plurality of die; and a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die. ### Claim 3 (depends on 2) The method according to claim 2, wherein the plurality of layer components further comprising: an electronic circuit substrate; and an elastomeric connector arranged between the semiconductor substrate and the electronic circuit substrate. ### Claim 4 (depends on 1) The method according to claim 1, wherein the mechanical compression load is applied by a clamping assembly, the clamping assembly comprising: a load application component that applies the mechanical compression load against the plurality of layer components of the integrated circuit assembly; a mechanical securing component that fastens each of the plurality of securing elements within the integrated circuit assembly. ### Claim 5 (depends on 1) The method according to claim 1, wherein: each of the plurality of securing elements comprises an elastic member arranged between an abutment portion of each securing element and a surface of one of the plurality of layers of the integrated circuit assembly, the elastic member absorbs expansion forces and contraction forces of the one or more of the plurality of layer components of the integrated circuit assembly. ### Claim 6 (depends on 1) The method according to claim 1, wherein: each of the plurality of securing elements comprise a plurality of elastic members disposed between a surface of abutment portion of the securing element and a surface of a layer component comprising a backing element of the integrated circuit assembly; fastening each of the plurality of securing elements into the integrated circuit assembly causes the surface of the abutment portion to come into contact with the plurality of the elastic members and compress the plurality of elastic members from a first uncompressed position to a second compressed position. ### Claim 7 (depends on 1) The method according to claim 1, further comprising: arranging a plurality of fastening members within or at a surface of an electronic circuit substrate of the integrated circuit assembly, wherein fastening the plurality of securing elements includes fastening one end of each of the plurality of securing element with one fastening member of the plurality of fastening members. ### Claim 8 (depends on 1) The method according to claim 1, wherein fastening the plurality of securing elements is triggered in response to achieving a desired mechanical compression load; ### Claim 9 (depends on 1) The method according to claim 1, wherein fastening the plurality of securing elements includes fastening each of the plurality of securing elements until a shoulder of each of the plurality of securing elements comes into contact with a surface of a fastening member. ### Claim 10 (depends on 1) The method according to claim 1, further comprising: synchronously fastening each of the plurality of securing elements within the integrated circuit assembly while the integrated circuit assembly is in a compressed state due to the applied mechanical compression load. ### Claim 11 (depends on 1) The method according to claim 1, wherein the mechanical compression load is maintained against the integrated circuit assembly until each of the plurality of securing elements is fastened to the integrated circuit assembly. ### Claim 12 (depends on 1) The method according to claim 1, further comprising: fabricating the plurality of orifices in each of the plurality of layer components of the integrated circuit assembly, wherein the fabricating the plurality of orifices includes positioning each of the plurality of orifices along each layer component of the integrated circuit layer according to a first predetermined pitch along a first direction and a second predetermined pitch along a second direction; aligning each of the plurality of layer components of the integrated circuit assembly according to the plurality of orifices in each of the plurality of layer components. ### Claim 13 (depends on 1) The method according to claim 1, wherein each orifice comprises a through hole that extends through each of the plurality of layer components of the integrated layer assembly. ### Claim 14 (depends on 1) The method according to claim 1, wherein each orifice comprises a through hole that extends through at least one of the plurality of layer components of the integrated layer assembly and terminates at a cavity within a terminal layer of the integrated circuit assembly. ### Claim 15 A method comprising: providing an integrated circuit assembly having a plurality of layer components, wherein the plurality of layer components comprises a plurality of orifices; arranging a plurality of securing elements within the plurality of orifices of the integrated circuit assembly; loading, by a load application component, a mechanical load against one or more of the plurality of layer components of the integrated circuit assembly; and fastening, by a mechanical securing component, each of the plurality of securing elements within the integrated circuit assembly while the mechanical load is continuously applied against the integrated circuit assembly. ### Claim 16 (depends on 15) The method according to claim 15, wherein at least one layer component of the plurality of layer components of the integrated circuit assembly comprises a semiconductor substrate having: a plurality of die formed with the semiconductor substrate; a circuit layer formed at each of the plurality of die; and a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die. ### Claim 17 (depends on 17) The method according to claim 17, wherein the plurality of layer components further comprising: an electronic circuit substrate; and an elastomeric connector arranged between the semiconductor substrate and the electronic circuit substrate. ### Claim 18 (depends on 15) The method according to claim 15, wherein: each of the plurality of securing elements comprises an elastic member arranged between an abutment portion of each securing element and a surface of one of the plurality of layers of the integrated circuit assembly. ### Claim 19 (depends on 15) The method according to claim 15, further comprising: a plurality of fastening members within or at a surface of an electronic circuit substrate of the integrated circuit assembly, wherein fastening the plurality of securing elements includes fastening one end of each of the plurality of securing element with one fastening member of the plurality of fastening members. ### Claim 20 (depends on 15) The method according to claim 15, wherein the elastic member comprises a plurality of Belville springs.