# US 2019/0172709 A1 · Systems and method for integrated devices on an engineered substrate

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- Number: US 2019/0172709 A1
- Document ID: US20190172709A1
- Status: Published application
- Kind: A1
- Application number: 16/207,793
- Filed: 2018-12-03
- Published: 2019-06-06
- Earliest claimed: 2017-12-06
- Assignees: QROMIS, Inc.
- Applicants: QROMIS, Inc.
- Inventors: Vladimir Odnoblyudov; Dilip Risbud; Ozgur Aktas; Cem Basceri
- Web page: https://patentgrep.com/patent/US20190172709A1

## CPC

- H10P 14/3251: {consisting of three or more layers}
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10D 84/05: using Group III-V technology
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/82: of only field-effect components
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 14/2908: {Nitrides}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3256: {Microstructure}
- H10P 14/3416: {Nitrides}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/357: {of FETs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
- H10D 88/01: {Manufacture or treatment}
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/81: Bodies
- H10P 14/2921: {being crystalline insulating materials}
- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 50/283: {by chemical means}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices.

## Claims

### Claim 1

A method of forming a plurality of devices comprising:
forming a substrate by:
providing a polycrystalline ceramic core;
encapsulating the polycrystalline ceramic core with a first adhesion shell;
encapsulating the first adhesion shell with a barrier layer;
forming a bonding layer on the barrier layer; and
forming a substantially single crystal layer coupled to the bonding layer;
forming a buffer layer coupled to the substantially single crystal layer;
forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices; and
forming the plurality of devices on the substrate by:
removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices; and
removing a portion of the buffer layer disposed between the plurality of devices.

### Claim 2 (depends on 1)

The method of claim 1 wherein the one or more epitaxial III-V layers comprise GaN.

### Claim 3 (depends on 1)

The method of claim 1 further comprising planarizing the plurality of devices on the substrate.

### Claim 4 (depends on 3)

The method of claim 3 wherein planarizing further comprises:
forming a dielectric layer on the plurality of devices; and
smoothing the plurality of devices using chemical-mechanical planarization.

### Claim 5 (depends on 1)

The method of claim 1 further comprising fabricating one or more interconnects between a first device of the plurality of devices and a second device of the plurality of devices.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
bonding a first surface on each of the plurality of devices to a temporary carrier, wherein the first surface is opposed to the substrate;
removing the substrate to expose a second surface on each of the devices;
forming a conducting layer on the second surface; and
bonding a carrier wafer to the conducting layer.

### Claim 7 (depends on 6)

The method of claim 6 further comprising removing one or more sections of the carrier wafer to form one or more backside contacts.

### Claim 8 (depends on 1)

The method of claim 1 wherein the plurality of devices comprises a depletion-mode high electron mobility transistor (HEMT), and an enhancement-mode HEMT.

### Claim 9 (depends on 1)

The method of claim 1 wherein the plurality of devices comprises a first depletion-mode high electron mobility transistor (HEMT), and a second depletion-mode HEMT.

### Claim 10 (depends on 1)

The method of claim 1 wherein the plurality of devices comprises a first enhancement-mode high electron mobility transistor (HEMT), and a second enhancement-mode HEMT.

### Claim 11 (depends on 1)

The method of claim 1 wherein the plurality of devices comprises a high electron mobility transistor (HEMT) and a vertical device.

### Claim 12

A method of forming a plurality of devices comprising:
forming a substrate by:
providing a polycrystalline ceramic core;
encapsulating the polycrystalline ceramic core with an adhesion shell;
encapsulating the adhesion shell with a barrier layer;
forming a bonding layer on the barrier layer; and
forming a substantially single crystal layer coupled to the bonding layer;
forming a conducting layer coupled to the substantially single crystal layer;
forming a buffer layer coupled to the conducting layer;
forming one or more epitaxial III-V layers on the buffer layer according to requirements for each of the plurality of devices; and
forming the plurality of devices by:
removing a portion of the one or more epitaxial layers and a portion of the buffer layer disposed between the plurality of devices to expose a portion of the conducting layer;
forming a contact coupled to a portion of the exposed portion of the conducting layer; and
removing a remaining exposed portion of the conducting layer not coupled to the contact.

### Claim 13 (depends on 12)

The method of claim 12 further comprising planarizing the plurality of devices on the substrate.

### Claim 14 (depends on 13)

The method of claim 13 wherein planarizing further comprises:
forming a dielectric layer on the plurality of devices; and
smoothing the plurality of devices using chemical-mechanical planarization.

### Claim 15 (depends on 12)

The method of claim 12 further comprising fabricating one or more interconnects between a first device of the plurality of devices and a second device of the plurality of devices.

### Claim 16 (depends on 12)

The method of claim 12 further comprising:
bonding a first surface on each of the plurality of devices to a temporary carrier, wherein the first surface is opposed to the substrate;
removing the substrate to expose a second surface on each of the devices;
forming a second conducting layer on the second surface; and
bonding a carrier wafer to the second conducting layer.

### Claim 17 (depends on 16)

The method of claim 16 further comprising removing one or more sections of the carrier wafer to form one or more backside contacts.

### Claim 18 (depends on 12)

The method of claim 12 wherein the plurality of devices comprises a high electron mobility transistor (HEMT) and a vertical device.

### Claim 19 (depends on 18)

The method of claim 18 wherein the HEMT comprises a depletion-mode HEMT or an enhancement-mode HEMT.

### Claim 20 (depends on 18)

The method of claim 18 wherein the vertical device comprises a vertical P-N diode or a vertical Schottky diode.