# US 2019/0172702 A1 · Semiconductor device and method for manufacturing semiconductor device

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- Number: US 2019/0172702 A1
- Document ID: US20190172702A1
- Status: Published application
- Kind: A1
- Application number: 16/255,941
- Filed: 2019-01-24
- Published: 2019-06-06
- Earliest claimed: 2012-02-08
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei YAMAZAKI
- Web page: https://patentgrep.com/patent/US20190172702A1

## CPC

- H10P 14/2901: {Materials}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 62/40: Crystalline structures
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/6314: {of a metallic layer}
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a highly reliable semiconductor device which includes a transistor including an oxide semiconductor. The semiconductor device includes an oxide semiconductor layer; a gate insulating layer provided over the oxide semiconductor layer; a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween; an insulating layer being in contact with part of an upper surface of the oxide semiconductor layer, covering a side surface of the gate insulating layer and a side surface and an upper surface of the gate electrode layer, and having a lower oxygen-transmitting property than the gate insulating layer; a sidewall insulating layer provided on the side surface of the gate electrode layer with the insulating layer provided therebetween; a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer.

## Claims

### Claim 1

(canceled)

### Claim 2

A semiconductor device comprising:
an oxide semiconductor layer;
a source electrode layer in contact with a first part of an upper surface of the oxide semiconductor layer and a first side surface of the oxide semiconductor layer;
a drain electrode layer in contact with a second part of the upper surface of the oxide semiconductor layer and a second side surface of the oxide semiconductor layer;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer;
a first insulating layer in contact with the gate insulating layer;
a second insulating layer covering a side surface and an upper surface of the gate electrode layer;
a first wiring layer in contact with an upper surface of the source electrode layer; and
a second wiring layer in contact with an upper surface of the drain electrode layer,
wherein the gate insulating layer comprises silicon oxide or silicon oxynitride,
wherein the first insulating layer comprises an oxide film comprising aluminum,
wherein the second insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, and
wherein a part of the first wiring layer in contact with the source electrode layer overlaps with the first side surface of the oxide semiconductor layer.

### Claim 3

A semiconductor device comprising:
an oxide semiconductor layer;
a source electrode layer in contact with a first part of an upper surface of the oxide semiconductor layer and a first side surface of the oxide semiconductor layer;
a drain electrode layer in contact with a second part of the upper surface of the oxide semiconductor layer and a second side surface of the oxide semiconductor layer;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer;
a first insulating layer in contact with the gate insulating layer;
a second insulating layer in contact with the first insulating layer, the second insulating layer covering a side surface and an upper surface of the gate electrode layer;
a first wiring layer in contact with an upper surface of the source electrode layer; and
a second wiring layer in contact with an upper surface of the drain electrode layer,
wherein the gate insulating layer comprises silicon oxide or silicon oxynitride,
wherein the first insulating layer comprises an oxide film comprising aluminum,
wherein the second insulating layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide,
wherein a part of the first wiring layer in contact with the source electrode layer overlaps with the first side surface of the oxide semiconductor layer, and
wherein a part of the second wiring layer in contact with the drain electrode layer overlaps with the second side surface of the oxide semiconductor layer.