# US 2019/0172684 A1 · Mechanical suppression of parasitic plasma in substrate processing chamber

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- Number: US 2019/0172684 A1
- Document ID: US20190172684A1
- Status: Published application
- Kind: A1
- Application number: 16/267,932
- Filed: 2019-02-05
- Published: 2019-06-06
- Earliest claimed: 2011-10-17
- Assignees: Lam Research Corporation
- Applicants: Lam Research Corporation
- Inventors: Douglas KEIL; Edward J. AUGUSTYNIAK; Karl Frederick LEESER; Mohamed SABRI
- Web page: https://patentgrep.com/patent/US20190172684A1

## CPC

- H01J 37/32495: {Means for protecting the vessel against plasma}
- C23C 16/45565: {Shower nozzles}
- H01J 37/3244: {Gas supply means}
- H01J 37/32623: {Mechanical discharge control means}
- H01J 37/32091: {the radio frequency energy being capacitively coupled to the plasma}
- H01J 37/3255: {Material}
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)

## Abstract

A system includes an electrode. The electrode includes a showerhead having a first stem portion and a head portion. A plurality of dielectric layers is vertically stacked between the electrode and a first surface of a conducting structure. The plurality of dielectric layers includes M dielectric layers arranged adjacent to the head portion and P dielectric portions arranged around the first stem portion. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap, and the third gap are selected to prevent parasitic plasma between the first surface and the electrode.

## Claims

### Claim 1

A system for reducing parasitic plasma in a semiconductor process, comprising:
an electrode, wherein the electrode includes a showerhead having a first stem portion and a head portion; and
a plurality of dielectric layers that is vertically stacked between the electrode and a first surface of a conducting structure, wherein the plurality of dielectric layers includes M dielectric layers arranged adjacent to the head portion and P dielectric portions arranged around the first stem portion, and wherein M and P are integers greater than one,
wherein the first surface and the electrode have different electrical potentials,
wherein the plurality of dielectric layers defines:
a first gap between the electrode and one of the plurality of dielectric layers,
a second gap between adjacent ones of the plurality of dielectric layers, and
a third gap between a last one of the plurality of dielectric layers and the first surface, and
wherein a number of the plurality of dielectric layers and sizes of the first gap, the second gap, and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.

### Claim 2 (depends on 1)

The system of claim 1, wherein the conducting structure is grounded.

### Claim 3 (depends on 1)

The system of claim 1, further comprising barriers arranged between radially outer ends of the plurality of dielectric layers to prevent incursion of deposition precursor species between the plurality of dielectric layers.

### Claim 4 (depends on 1)

The system of claim 1, wherein diameters of each of the plurality of dielectric layers decrease as a distance increases between the electrode and a respective one of the plurality of dielectric layers.

### Claim 5 (depends on 1)

The system of claim 1, wherein each of the plurality of dielectric layers comprises a radially inner portion having a first thickness in an axial direction and a protruding portion that extends radially outwardly and has a second thickness in the axial direction.

### Claim 6 (depends on 5)

The system of claim 5, wherein a difference between the first thickness and the second thickness is equal to the second gap.

### Claim 7 (depends on 1)

The system of claim 1, wherein the semiconductor process comprises plasma-enhanced chemical vapor deposition (PECVD).

### Claim 8 (depends on 1)

The system of claim 1, further comprising a pedestal including a pedestal platen that supports a substrate and that is made of a non-conducting material.

### Claim 9 (depends on 8)

The system of claim 8, wherein, during the semiconductor process, the conducting structure is connected to RF ground and the electrode is connected to an RF bias.

### Claim 10 (depends on 8)

The system of claim 8, further comprising:
a collar that is connected to the first surface; and
an adapter that is connected to the collar.

### Claim 11 (depends on 10)

The system of claim 10, wherein the first surface, the collar and the adapter comprise aluminum.

### Claim 12 (depends on 8)

The system of claim 8, wherein the pedestal platen comprises ceramic, the conducting structure comprises a conducting disk, the electrode comprises wire mesh, and each of the plurality of dielectric layers comprises a disk.

### Claim 13 (depends on 1)

The system of claim 1, wherein the conducting structure comprises:
a second stem portion arranged around the first stem portion and the P dielectric portions; and
a disk portion that projects radially outwardly from the second stem portion.

### Claim 14

A showerhead system for a semiconductor process, comprising:
a showerhead;
a first surface having a different electrical potential than the showerhead; and
a dielectric structure that includes a plurality of spaced dielectric layers and that is arranged between the first surface and the showerhead,
wherein a number of the plurality of spaced dielectric layers and spacing between the plurality of spaced dielectric layers are selected to prevent parasitic plasma between the first surface and the showerhead during the semiconductor process.

### Claim 15 (depends on 14)

The showerhead system of claim 14, wherein the first surface comprises a surface of a processing chamber.

### Claim 16 (depends on 14)

The showerhead system of claim 14, wherein the showerhead comprises a first stem portion and a head portion.

### Claim 17 (depends on 16)

The showerhead system of claim 16, wherein the plurality of spaced dielectric layers comprises M dielectric layers that are arranged adjacent to the head portion and around the first stem portion and P dielectric layers that surround the first stem portion of the showerhead.

### Claim 18 (depends on 17)

The showerhead system of claim 17, further comprising barriers arranged between radially outer ends of the M dielectric layers to prevent incursion of deposition precursor species between the M dielectric layers.

### Claim 19 (depends on 17)

The showerhead system of claim 17, wherein the first surface comprises:
a second stem portion surrounding the P dielectric layers and the first stem portion of the showerhead; and
a disk portion that projects radially outwardly from one end of the second stem portion and that is arranged adjacent to the M dielectric layers.

### Claim 20 (depends on 19)

The showerhead system of claim 19, wherein:
the M dielectric layers provide a first gap between the showerhead and the M dielectric layers, a second gap between adjacent ones of the M dielectric layers, and a third gap between the M dielectric layers and the first surface; and
the P dielectric layers provide a fourth gap between the showerhead and the P dielectric layers, a fifth gap between adjacent ones of the P dielectric layers, and a sixth gap between the P dielectric layers and the first surface.