# US 2019/0172545 A1 · Error characterization and mitigation for 16nm mlc nand flash memory under total ionizing dose effect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172545 A1 - Document ID: US20190172545A1 - Status: Published application - Kind: A1 - Application number: 16/259,143 - Filed: 2019-01-28 - Published: 2019-06-06 - Earliest claimed: 2015-10-19 - Assignees: California Institute of Technology - Applicants: California Institute of Technology - Inventors: Yue Li; Jehoshua Bruck - Web page: https://patentgrep.com/patent/US20190172545A1 ## CPC - G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/10: Programming or data input circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 2029/0409: {Online test} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A radiation hardened NAND flash memory data storage device suitable for space flight having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count. Methods of operating the data storage device are also described. ## Claims ### Claim 1 A radiation hardened NAND flash memory data storage apparatus suitable for space flight, the apparatus comprising: a flash memory; a charge pump operatively configured for page reading, page programming, and block erasure of memory cells in the flash memory; an error correcting code (ECC) block including program code for rank modulation coding and decoding of data to and from the flash memory; and a memory controller microcontroller configured for selecting a scrubbing mode for the flash memory from a plurality of scrubbing modes based on a current error count for one or more data operations and a program cycles count for the flash memory. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the plurality of scrubbing modes comprises an MLC (multi-level cell) scrubbing scheme, an E-SLC (enhanced single-level cell) scrubbing scheme, and an SLC-IPR (single level cell in-place rewriting) scrubbing scheme. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the MLC scrubbing scheme is configured to use sequential MLC programming to set a charge level of each cell of the memory according to four or more charge levels. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the E-SLC scrubbing scheme is configured to use only two states of available charge level states in each cell of the memory. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein the SLC-IPR scrubbing scheme is configured to use block erasure for rewriting a cell and in-place rewriting of charge level states in each cell of the memory. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein at least one scrubbing mode of the plurality of scrubbing modes uses only a high voltage state and a low voltage state for cells of the memory or uses two voltage levels for each of the memory cells out of four voltage levels that are available for each of the memory cells. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein at least one of the plurality of scrubbing modes is configured to perform a data storage operation without first performing a block erasure operation. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the ECC block includes programmed operations for translating between received symbols and error-corrected symbols. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the ECC block includes lookup tables for codewords. ### Claim 10 (depends on 1) The apparatus of claim 1, further comprising: shielding around the flash memory. ### Claim 11 A computer implemented method of operating radiation hardened NAND flash memory data storage apparatus suitable for space flight, the method comprising: receiving a current error count at a memory controller microcontroller for one or more data operations and a program cycles count for a flash memory having memory cells, the current error count indicating errors detected in the flash memory; selecting a scrubbing mode based upon the current error count and the program cycles count; scrubbing the flash memory in accordance with the selected scrubbing mode; and coding and decoding data to and from the flash memory using rank modulation. ### Claim 12 (depends on 11) The method of claim 11, wherein the selected scrubbing mode comprises one of an MLC (multi-level cell) scrubbing scheme, an E-SLC (enhanced single-level cell) scrubbing scheme, and an SLC-IPR (single level cell in-place rewriting) scrubbing scheme. ### Claim 13 (depends on 12) The method of claim 12, wherein the MLC scrubbing scheme uses sequential MLC programming to set a charge level of each cell of the memory according to four or more charge levels. ### Claim 14 (depends on 12) The method of claim 12, wherein the E-SLC scrubbing scheme uses only two states of available charge level states in each cell of the memory. ### Claim 15 (depends on 12) The method of claim 12, wherein the SLC-IPR scrubbing scheme does not use block erasure for rewriting a cell and uses in-place rewriting of charge level states in each cell of the memory. ### Claim 16 (depends on 11) The method as in claim 11, wherein the selected scrubbing mode uses only a high voltage state and a low voltage state for cells of the memory or uses two voltage levels for each of the memory cells out of four voltage levels that are available for each of the memory cells. ### Claim 17 (depends on 11) The method as in claim 11, wherein the selected scrubbing mode includes performing a data storage operation without first performing a block erasure operation. ### Claim 18 (depends on 11) The method of claim 11, wherein the coding and decoding includes translating between received symbols and error-corrected symbols. ### Claim 19 (depends on 11) The method of claim 11, wherein the coding and decoding includes accessing lookup tables for codewords.