# US 2019/0172537 A1 · Solid state drive architectures

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- Number: US 2019/0172537 A1
- Document ID: US20190172537A1
- Status: Published application
- Kind: A1
- Application number: 16/255,320
- Filed: 2019-01-23
- Published: 2019-06-06
- Earliest claimed: 2012-11-20
- Assignees: Thstyme Bermuda Limited
- Applicants: Thstyme Bermuda Limited
- Inventors: Charles I. Peddle; Martin Snelgrove; Robert Neil McKenzie; Xavier Snelgrove
- Web page: https://patentgrep.com/patent/US20190172537A1

## CPC

- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/1036: Life time enhancement
- G06F 2212/225: Hybrid cache memory, e.g. having both volatile and non-volatile portions
- G06F 2212/262: configured as RAID
- G06F 2212/283: Plural cache memories
- G06F 2212/284: being distributed
- G06F 2212/312: In storage controller
- G06F 2212/313: In storage device
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/10: Programming or data input circuits
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

## Claims

### Claim 1

A solid state drive (SSD) comprising:
dynamic random access memory (DRAM);
flash memory;
a solid state drive (SSD) controller; and
a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM,
wherein the SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

### Claim 2 (depends on 1)

The SSD of claim 1, wherein the SSD controller comprises:
a non-volatile memory express (NVMe) controller to receive commands from the computing device to access the SSD;
a command block to receive and store the commands, wherein a command includes a logical block address and a command word;
a memory manager to manage data transfer into and out of the DRAM based on a mapping between the logical block address of the command and a pointer to a location in the DRAM;
a logical flash controller to manage data transfer between the SSD and the computing device;
at least one flash interface controller to buffer data to be written to multiple flash die from the DRAM; and
a flash controller per flash interface controller paired with a flash die to manage data access into and out of the flash die.

### Claim 3 (depends on 2)

The SSD of claim 2, wherein the at least one flash interface controller comprises multiple flash interface controllers.

### Claim 4 (depends on 3)

The SSD of claim 3, wherein multiple flash die are written to in parallel.

### Claim 5 (depends on 2)

The SSD of claim 2, wherein the SSD controller further comprises a DRAM controller to manage data access to the DRAM.

### Claim 6 (depends on 2)

The SSD of claim 2, wherein the flash interface controller maps the logical block address to locations on corresponding flash die.

### Claim 7 (depends on 1)

The SSD of claim 1, in which data access to the DRAM is implemented at full interface speed.

### Claim 8

A method, comprising:
receiving from a computing device, a command to access a solid state drive (SSD), wherein the command includes a logical block address and a command word;
storing the command in a command block of an SSD controller;
determining, from a logical record (LR) table stored in a memory manager of the SSD controller, whether the logical block address maps to a pointer to a location on dynamic random access memory (DRAM); and
when the logical block address maps to a pointer in the DRAM, executing the command in the DRAM based on the mapping, while preventing access of the computing device to flash memory of the SSD.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
the command is a read command; and
the method further comprises:
determining from the LR table, with the memory manager, if data associated with the command word is stored in DRAM;
when the data associated with the command word is stored in DRAM, transferring the data from the DRAM to the computing device; and
when the data associated with the command word is not stored in DRAM:
sending the command word to a flash interface controller;
determining at the flash interface controller a location on the flash memory where the data is stored; and
transferring the data from the flash memory to the computing device.

### Claim 10 (depends on 9)

The method of claim 9, wherein data is stored on the DRAM in 32k packets.

### Claim 11 (depends on 8)

The method of claim 8, wherein:
the command is a write command; and
the method further comprises:
when the logical block address maps to a location on the DRAM, storing data associated with the command word in DRAM; and
when the logical block address does not map to a location on the DRAM:
generating a mapping between the logical block address of the command and a new unused location on the DRAM; and
storing the data associated with the command on the DRAM in the new unused location; and
reporting to the computing device that the write command is complete.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
holding data associated with the command in DRAM;
determining when the DRAM has a threshold amount of full blocks; and
when the DRAM has the threshold amount of full blocks, transferring the full blocks to the flash memory, wherein the full blocks are transferred to the flash memory independent of any received command.

### Claim 13 (depends on 12)

The method of claim 12, wherein transferring the full blocks to the flash memory comprises:
dividing the data in the full blocks into various portions;
buffering the various portions in different flash interface controllers; and
for each flash interface controller:
sequentially initiating writes to each corresponding flash die via a flash controller coupled to a flash die.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
after a write has been initialized on a first flash die, initiating a write on a second flash die before the write to the first flash die is complete; and
when data remains in the buffer and the write on the first flash die has terminated, initiating another sequential write on the first flash die.

### Claim 15 (depends on 14)

The method of claim 14, wherein writes to each flash die are at three or four page increments.

### Claim 16

A solid state drive (SSD) comprising:
dynamic random access memory (DRAM);
flash memory comprising:
multiple flash die;
at least one flash interface controller to buffer data to be written to a subset of the multiple flash die from the DRAM; and
a flash controller per flash interface controller and paired with a flash die to manage data access into and out of the flash die,
a peripheral component interconnect express (PCIe) bus coupling the SSD to a computing device; and
a solid state drive (SSD) controller comprising:
a non-volatile memory express (NVMe) controller to receive commands to access the SSD;
a command block to receive and store the commands, wherein a command includes a logical block address and a command word;
a memory manager to manage data transfer into and out of the DRAM based on a mapping between the logical block address of the command and a pointer to a location in the DRAM;
a logical flash controller to manage data transfer between the SSD and the computing device;
wherein less than all writes to the SSD are written to the flash memory.

### Claim 17 (depends on 16)

The SSD of claim 16, wherein the DRAM is the only memory accessible by the computing device.

### Claim 18 (depends on 16)

The SSD of claim 16, wherein the NVMe controller receives multiple commands and stores the multiple commands in a command buffer of the command block.

### Claim 19 (depends on 16)

The SSD of claim 16, wherein the command block sends a record of execution of the command.

### Claim 20 (depends on 16)

The SSD of claim 16, wherein pages of the flash die are identified as having errors and eliminated from a block while other pages in the block remain in use to increase the lifetime of the flash memory by at least 10 times that of flash memory that eliminates an entire sector when an error is detected in a page within the sector.