# US 2019/0172536 A1 · Methods for Programming 1-R Resistive Change Element Arrays

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- Number: US 2019/0172536 A1
- Document ID: US20190172536A1
- Status: Published application
- Kind: A1
- Application number: 16/260,080
- Filed: 2019-01-28
- Published: 2019-06-06
- Earliest claimed: 2015-01-22
- Assignees: Nantero, Inc.
- Applicants: Nantero, Inc.
- Inventors: Claude L. Bertin; Lee Cleveland
- Web page: https://patentgrep.com/patent/US20190172536A1

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/0038: {Power supply circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2213/71: Three dimensional array
- G11C 2213/72: Array wherein the access device being a diode
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.

## Claims

### Claim 1

A method for adjusting at least one resistive element within a resistive change element array, comprising:
providing a resistive change element array, said resistive change element array comprising:
a plurality of word lines;
a plurality of bit lines; and
a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communications with a bit line;
selecting a first subset of said plurality of resistive change elements to be adjusted into a RESET state and selecting a second subset of said plurality of resistive change elements to be adjusted into a SET state, each resistive change element in said first subset and said second subset being associated with one of said plurality of word lines and one of said plurality of bit lines;
driving all of said plurality of word lines and all of said plurality of bit lines to zero volts;
driving said word lines associated with said first selected subset and said second selected subset of resistive change elements to a first preselected programming voltage, wherein said first preselected programing voltage provides a first programing current to flow through said first selected subset and said second selected subset of resistive change elements and wherein said first programing current ensures that said resistive change elements within said first selected subset and said second selected subset are all in a RESET state;
floating all of said word lines and bit lines;
pre-charging all of said bit lines to a second preselected programming voltage;
driving said bit lines associated with said second selected subset of resistive change elements to a third preselected programming voltage;
driving said word lines associated with said second selected subset of resistive change element to zero volts, providing a second programming current to flow through said second selected subset of resistive change elements and wherein said second programming current adjusts all of said resistive change elements within said second selected subset into a SET state.

### Claim 2 (depends on 1)

The method of claim 1 wherein said SET state is characterized by a resistive change element having a first nonvolatile electrical resistance value and said RESET state is characterized by a resistive change element having a second nonvolatile electrical resistance value.

### Claim 3 (depends on 2)

The method of claim 2 wherein said first nonvolatile electrical resistance value is lower than said second nonvolatile electrical resistive value.

### Claim 4 (depends on 2)

The method of claim 2 wherein said first nonvolatile electrical resistance value corresponds to a first logic value and said second nonvolatile electrical resistance value corresponds to a second logic value.

### Claim 5 (depends on 1)

The method of claim 1 wherein said first programing current flows through said resistive change elements from said first terminal to said second terminal.

### Claim 6 (depends on 1)

The method of claim 1 wherein said second programing current flows through said resistive change elements from said second terminal to said first terminal.

### Claim 7 (depends on 1)

The method of claim 1 wherein said first programming current flows in a first direction through said resistive change elements and said second programing current flows in a second direction through said resistive change elements, said second direction opposite of said first direction and said resistive change elements operating in a bi-polar programming mode.

### Claim 8 (depends on 1)

The method of claim 1 wherein said first programming current and said second programming current flow in the same direction through said resistive change elements and said resistive change elements operating in a uni-polar programming mode.

### Claim 9 (depends on 1)

The method of claim 1 wherein said resistive change element array can be used with programming current in either direction through said resistive change elements.

### Claim 10 (depends on 1)

The method of claim 1 wherein said second preselected programing voltage is half of said third preselected programming voltage.

### Claim 11 (depends on 1)

The method of claim 1 wherein said second preselected programing voltage provides sufficient bias to those resistive change elements outside of said second selected subset to prevent those resistive change elements from changing resistive state while said third preselected programing voltage is applied to said second subset of resistive change elements.

### Claim 12 (depends on 1)

The method of claim 1 wherein said third preselected programming voltage is on the order of two volts.

### Claim 13 (depends on 1)

The method of claim 1 wherein the number of said word lines is 128 and the number of said bit lines is 256.

### Claim 14 (depends on 1)

The method of claim 1 wherein the minimum resistance value of said resistance change elements is 1 megaohm and the maximum resistance value of said resistance change elements is 20 megaohms.

### Claim 15 (depends on 1)

The method of claim 1 wherein the minimum resistance value of said resistance change element is 100 kilo-ohms and the maximum resistance value of said resistance change elements is 2 megaohms.

### Claim 16 (depends on 1)

The method of claim 1 wherein said resistive change elements are two-terminal nanotube switching elements.

### Claim 17 (depends on 16)

The method of claim 16 wherein said two-terminal nanotube switching elements comprise a nanotube fabric.

### Claim 18 (depends on 1)

The method of claim 1 wherein said resistive change elements are metal oxide memory elements.

### Claim 19 (depends on 1)

The method of claim 1 wherein said resistive change elements are phase change memory elements.

### Claim 20 (depends on 1)

The method of claim 1 wherein said resistive change element array is a memory array.