# US 2019/0172522 A1 · SRAM Configuration Cell for Low-Power Field Programmable Gate Arrays

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172522 A1
- Document ID: US20190172522A1
- Status: Published application
- Kind: A1
- Application number: 16/178,093
- Filed: 2018-11-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Microsemi SoC Corporation
- Applicants: Microsemi SoC Corp.
- Inventors: Jonathan W. Greene; John McCollum
- Web page: https://patentgrep.com/patent/US20190172522A1

## CPC

- G11C 11/412: using field-effect transistors only
- H03K 19/1776: for memories
- G11C 11/419: Read-write [R-W] circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.

## Claims

### Claim 1

A random-access memory cell comprising:
first and second voltage supply nodes;
first and second complementary output nodes;
first and second complementary bit lines associated with the memory cell;
a word line associated with the memory cell;
a first pair of series-connected p-channel hybrid FinFET transistors connected between the first power supply node and the first output node;
a first pair of series-connected n-channel hybrid FinFET transistors connected between the first output node and the second power supply node;
a second pair of series-connected p-channel hybrid FinFET transistors connected between the first power supply node and the first output node;
a second pair of series-connected n-channel hybrid FinFET transistors connected between the first output node and the second power supply node;
gates of the first pair of series-connected p-channel hybrid FinFET transistors and the first pair of series-connected n-channel hybrid FinFET transistors connected to the second output node;
gates of the second pair of series-connected p-channel hybrid FinFET transistors and the second pair of series-connected n-channel hybrid FinFET transistors connected to the first output node;
the first bit line coupled to the first output node, and
the second bit line coupled to the second output node.

### Claim 2 (depends on 1)

The random-access memory cell of claim 1 wherein:
the first bit line is coupled to the first output node through a first n-channel FinFET select transistor; and
the second bit line coupled to the second output node through a second re -channel hybrid FinFET select transistor.

### Claim 3 (depends on 1)

The static random-access memory cell of claim 1 further comprising control circuitry configured to supply a programming potential to the first voltage supply node during a programming mode and supply an operating potential higher than the programming potential during a read mode.

### Claim 4 (depends on 1)

The static random-access memory cell of claim 1 further comprising an re -channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes.

### Claim 5

A static random-access memory cell comprising:
first and second voltage supply nodes;
first and second complementary output nodes;
first and second complementary bit lines associated with the memory cell;
a word line associated with the memory cell;
a first pair of series-connected p-channel hybrid FinFET transistors connected between the first voltage supply node and the first output node;
a first pair of series-connected n-channel hybrid FinFET transistors connected between the second voltage supply node and the first output node;
a second pair of series-connected p-channel hybrid FinFET transistors connected between the first voltage supply node and the second output node;
a second pair of series-connected n-channel hybrid FinFET transistors connected between the second voltage supply node and the second output node;
the first pair of series-connected p-channel hybrid FinFET transistors and the first pair of series-connected n-channel hybrid FinFET transistors each having gates connected together to the second output node, and the second pair of series-connected p -channel hybrid FinFET transistors and the second pair of series-connected n-channel hybrid FinFET transistors each having gates connected together to the second output node;
an n-channel hybrid FinFET transistor switch having a gate connected to one of the first and second output nodes;
a first n-channel hybrid FinFET select transistor coupled between the first bit line and the first output node;
a second n-channel hybrid FinFET select transistor coupled between the second bit line and the second output node; and
the first and second n-channel hybrid FinFET select transistors each having a gate coupled to the word line.

### Claim 6 (depends on 5)

The static random-access memory cell of claim 5 further comprising control circuitry configured to supply a programming potential to the first voltage supply node during a programming mode and supply an operating potential higher than the programming potential during a read mode.

### Claim 7 (depends on 5)

The static random-access memory cell of claim 5 further comprising an re -channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes.

### Claim 8

A method of operating a random-access memory cell formed from pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors coupled to a pair of complementary bit lines through a pair of hybrid FinFET select transistors, the method comprising:
during a programming mode of operation powering the memory cell with a first voltage potential and placing one of the first potential and 0V on a first one of the bit lines and the other one of the first potential and 0V on a second one of the bit lines; and
during a read mode of operation powering the memory cell with a second voltage potential higher than the first voltage potential and placing half of the second voltage potential on both of the complementary bit lines.

### Claim 9 (depends on 8)

The method of claim 8 further comprising:
during the programming mode of operation selecting the memory cell for programming by placing the first voltage potential on gates of the pair of hybrid FinFET select transistors or deselecting the memory cell for programming by placing 0V on the gates of the pair of hybrid FinFET select transistors.

### Claim 10

An integrated circuit comprising:
a plurality of first random-access memory cells each including first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with each first memory cell, and a word line associated with each first memory cell, each first memory cell further including pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node; and
a plurality of second random-access memory cells each including first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with each second memory cell, and a word line associated with each second memory cell, each second memory cell further including cross-coupled p-channel and n-channel hybrid FinFET transistors connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein:
the first random-access memory cells each further comprise an n-channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes; and
the second random-access memory cells each further comprise an n-channel hybrid FinFET switch transistor having a gate coupled to one of the first and second output nodes.

### Claim 12 (depends on 10)

The integrated circuit of claim 10 further comprising control circuitry configured to supply a programming potential to the first voltage supply node plurality of the first random-access memory cells during a programming mode and supply an operating potential higher than the programming potential of the plurality of first random -access memory cells during a read mode.