# US 2019/0172519 A1 · Apparatuses and methods for configurable command and data input circuits for semiconductor memories

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- Number: US 2019/0172519 A1
- Document ID: US20190172519A1
- Status: Published application
- Kind: A1
- Application number: 16/273,598
- Filed: 2019-02-12
- Published: 2019-06-06
- Earliest claimed: 2017-05-09
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hyun Yoo Lee; Kang-Yong Kim; John D. Porter
- Web page: https://patentgrep.com/patent/US20190172519A1

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 7/106: {Data output latches}
- G11C 7/1066: {Output synchronization}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/225: {Clock input buffers}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 2207/2227: Standby or low power modes
- G11C 2207/2272: Latency related aspects
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

## Claims

### Claim 1

An apparatus, comprising:
a plurality of driver circuits, each driver circuit of the plurality of driver circuits configured to receive first and second internal strobe signals and receive first and second enable signals, and each driver circuit of the plurality of driver circuits configured to provide a first driver signal based on the first internal strobe signal responsive to an active first enable signal and to provide a second driver signal based on the first internal strobe signal responsive to an active second enable signal, and further configured to provide a third driver signal based on the second internal strobe signal responsive to the active first enable signal and to provide a fourth driver signal based on the second internal strobe signal responsive to the active second enable signal; and
a plurality of data receiver circuits, each data receiver circuit of the plurality of data receiver circuits configured to receive the first, second, third, and fourth driver signals from a respective driver circuit of the plurality of driver circuits and to receive respective data and a data reference voltage, each data receiver circuit of the plurality of data receiver circuits further configured to sample the respective data relative to the data reference voltage having a first voltage with, a first power and to sample the respective data relative to the data reference voltage having a second voltage higher than the first voltage with a second power that is higher than the first power.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein each data receiver circuit of the plurality of data receiver circuits comprises:
a first power switch configured to be coupled to a power supply and configured to provide power from the power supply when activated by the first driver signal;
a second power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the second driver signal;
a first sampler circuit coupled to the first and second power switches and configured to receive data and a data reference voltage and to receive the first, second and third driver signals, the first sampler circuit configured to sample the data responsive to the first and third driver signals to provide first internal data when power is provided at least by the first power switch;
a third power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the third driver signal;
a fourth power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the fourth driver signal;
a second sampler circuit coupled to the third and fourth power switches and configured to receive the data and the data reference voltage and to receive the first, third, and fourth driver signals, the second sampler circuit configured to sample the data responsive to the third and fourth driver signals to provide second internal data when power is provided at least by the third power switch.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first sampler circuit comprises:
a differential amplifier coupled to the first and second power switches, the differential amplifier configured to compare the data and the data reference voltage and. provide an internal data signal based on the comparison when power is provided at least by the first power switch, the differential amplifier including first and second output nodes and the internal data signal provided at the first output node; and
a latch circuit coupled to the differential amplifier and configured to latch the complementary voltages at the first and second output nodes of the differential amplifier when activated by the third driver signal.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the first, second, third, and fourth power switches each comprises a p-channel field effect transistor.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the second power switch is activated by the second driver signal when the second enable signal is active and the fourth power switch is activated by the fourth driver signal when the second enable signal is active to provide the second power higher than the first power.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein each driver circuit of the plurality of driver circuits comprises:
a first driver logic circuit configured to receive the first internal strobe signal, and the first and second enable signals, the first driver logic circuit configured to provide the first internal strobe signal as the first driver signal responsive to an active first enable signal and further configured to provide the first internal strobe signal as the second driver signal responsive to an active second enable signal; and
a second driver logic circuit configured to receive the second internal strobe signal, and the first and second enable signals, the second driver logic circuit configured to provide the second internal strobe signal as the third driver signal responsive to an active first enable signal and further configured to provide the second internal strobe signal as the fourth driver signal responsive to an active second enable signal,

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising a divider and driver circuit configured to receive first and second strobe signals having a first clock frequency and provide the first internal strobe signal and the second internal strobe signal having a second clock frequency that is one-half of the first clock frequency.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein each data, receiver circuit of the plurality of data receiver circuits comprises:
a first sampler circuit configured to sample the data responsive to the first and second driver signals, and selectively provide first internal data; and
a second sampler circuit configured to sample the data responsive to the third and fourth driver signals to selectively provide second internal data.

### Claim 9 (depends on 1)

The apparatus of claim 1, further comprising:
a first power switch configured to be coupled to a power supply and configured to provide power from the power simply when activated by the first driver signal;
a second power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the second driver signal;
a third power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the third, driver signal; and
a fourth power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the fourth driver signal.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein each data receiver circuit of the plurality of data receiver circuits comprises:
a first sampler circuit configured to provide first internal data when power is provided at least by the first power switch; and
a second sampler circuit configured to provide second internal data when power is provided, at least by the third power switch.

### Claim 11

An apparatus, comprising:
a driver circuit configured to:
receive first and second internal strobe signals and first and second, enable signals,
provide a first driver signal based on the first internal strobe signal responsive to an active first enable signal,
provide a second driver signal based on the first internal strobe signal responsive to an active second enable signal, and
provide a third driver signal based on the second internal strobe signal responsive to the active first enable signal, and
provide a fourth driver signal based on the second internal strobe signal responsive to the active second enable signal; and
a data receiver circuit configured to:
receive the first, second, third, and fourth driver signals from the driver circuit,
receive data and a data reference voltage,
sample the data relative to the data, reference voltage having a first voltage with a first power, and
sample the data relative to the data reference voltage having a second voltage higher than the first voltage with a second power that is higher than the first power.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising:
a first power switch, configured to be coupled to a power supply and configured to provide power from the power supply when activated by the first driver signal; and
a second power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the second driver signal.

### Claim 13 (depends on 12)

The apparatus of claim 12, further comprising:
a third power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the third driver signal; and
a fourth power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the fourth driver signal.

### Claim 14 (depends on 13)

The apparatus of claim 13, further comprising:
a first sampler circuit coupled to the first and second power switches and configured to provide first internal data when power is provided at least by the first power switch; and
a second sampler circuit coupled to the third and fourth power switches and configured to provide second internal data when power is provided at least by the third power switch.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the first sampler circuit comprises:
a first differential amplifier coupled to the first and second power switches; and
a first latch circuit coupled to the first differential amplifier, and
wherein the second sampler circuit comprises:
a second differential amplifier coupled to the third and fourth power switches; and
a second latch circuit coupled to the second differential amplifier.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the first differential amplifier is configured to compare the data and the data reference voltage and provide a first internal data signal based on the comparison when power is provided at least by the first power switch, and
wherein the second differential amplifier is configured to compare the data and the data reference voltage and provide a second internal data signal based on the comparison when power is provided at least by the third power switch.

### Claim 17

An apparatus, comprising:
a driver circuit configured to:
receive first and second internal strobe signals and first and second enable signals,
provide first and second driver signals based on the first and second internal strobe signals, respectively; and
a data receiver circuit configured to:
receive the first and second driver signals from the driver circuit,
receive data and a data reference voltage,
sample the data relative to the data reference voltage having a first voltage with a first power, and
sample the data relative to the data reference voltage having a second voltage higher than the first voltage with a second power that is higher than the first power.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the driver circuit is further configured to provide third and fourth driver signals based on the first and second internal strobe signals, respectively.

### Claim 19 (depends on 1)

The apparatus of claim 1S, wherein the driver circuit is further configured to:
provide the first and second driver signals based on the first and second internal strobe signals, respectively, and responsive to an active first enable signal, and
provide third and fourth driver signals based on the first, and second internal strobe signals, respectively, and responsive to an active second enable signal.

### Claim 20 (depends on 17)

The apparatus of claim 17, further comprising;
a first power switch configured to be coupled to a power supply and configured to provide power from the power supply when activated by the first driver signal;
a first differential amplifier coupled to the first power switch and configured to compare the data and the data reference voltage and provide a first internal data signal based on the comparison when, power is provided at least by the first power switch;
a second power switch configured to be coupled to the power supply and configured to provide power from the power supply when activated by the second driver signal; and
a second differential amplifier coupled to the second power switch and configured to compare the data and the data reference voltage and provide a second internal data signal based on the comparison when power is provided at least by the second power switch.