# US 2019/0172516 A1 · Electronic device performing training on memory device by rank unit and training method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172516 A1
- Document ID: US20190172516A1
- Status: Published application
- Kind: A1
- Application number: 16/034,848
- Filed: 2018-07-13
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: YONGSEOB KIM
- Web page: https://patentgrep.com/patent/US20190172516A1

## CPC

- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation
- G11C 11/4023: {using field effect transistors}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/4099: Dummy cell treatment; Reference voltage generators
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1093: {Input synchronization}
- G11C 8/00: Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413)
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An electronic device includes a memory device including first and second ranks, and a system-on-chip that exchanges data with the memory device. The system-on-chip loads a first training code to the first rank and performs a first training operation on the second rank using the first training code loaded to the first rank, and loads the first training code to the second rank and performs a second training operation on the first rank using the first training code loaded to the second rank. The system-on-chip generates a first reference voltage for sampling output data of the first rank, and generates a second reference voltage for sampling output data of the second rank. The first and second reference voltages are generated based on a first result of performing the first training operation on the second rank, and a second result of performing the second training operation on the first rank.

## Claims

### Claim 1

An electronic device, comprising:
a memory device comprising a first rank and a second rank; and
a system-on-chip that exchanges data with the memory device,
wherein the system-on-chip loads a first training code to the first rank and performs a first training operation on the second rank using the first training code loaded to the first rank, and loads the first training code to the second rank and performs a second training operation on the first rank using the first training code loaded to the second rank,
wherein the system-on-chip generates a first reference voltage for sampling output data of the first rank, and generates a second reference voltage for sampling output data of the second rank,
wherein the first reference voltage and the second reference voltage are generated based on a first result of performing the first training operation on the second rank, and a second result of performing the second training operation on the first rank.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein, before performing the first and second training operations, the system-on-chip disables or adjusts a rank interleaving mode of the memory device.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the first rank corresponds to a memory region in a first die, and the second rank corresponds to a memory region in a second die.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the system-on-chip comprises:
a memory controller that controls the memory device and generates the first and second reference voltages,
wherein voltage levels of the first and second reference voltages are adjusted according to the first and second results of performing the first and second training operations.

### Claim 5 (depends on 4)

The electronic device of claim 4, wherein the memory controller comprises:
a data receiver that samples the output data of the first rank and the output data of the second rank using the first and second reference voltages; and
a multi-reference voltage generator that selectively provides the first reference voltage and the second reference voltage to the data receiver in synchronization with a rank interleaving period.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the multi-reference voltage generator comprises;
a first reference voltage generator that generates the first reference voltage, wherein the first reference voltage is adjusted according to the second result of performing the second training operation on the first rank;
a second reference voltage generator that generates the second reference voltage, wherein the second reference voltage is adjusted according to the first result of performing the first training operation on the second rank;
a selection switch that selects one of the first reference voltage and the second reference voltage to be transferred to the data receiver; and
a voltage reference controller that controls the selection switch in synchronization with the rank interleaving period.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the system-on-chip further comprises:
a static random access memory (SRAM) to which a second training code for training the memory device is loaded.

### Claim 8 (depends on 7)

The electronic device of claim 7, wherein the system-on-chip executes the first training code loaded to the memory device after performing a coarse training operation on the memory device by executing the second training code.

### Claim 9 (depends on 1)

The electronic device of claim 1, further comprising:
a storage device that stores values of voltage levels of the first and second reference voltages, wherein the first and second reference voltages are adjusted according to the first and second results of the first and second training operations.

### Claim 10 (depends on 9)

The electronic device of claim 9, Wherein the system-on-chip receives the values of the voltage levels of the first and second reference voltages from the storage device, and initializes the memory device using the received values.

### Claim 11

A training method of an electronic device comprising a system-on-chip and a memory device, the method comprising:
disabling a rank interleaving mode of the memory device;
loading a training code to a first rank of the memory device;
performing a first training operation on a second rank of the memory device by executing the training code loaded to the first rank;
loading the training code to the second rank;
performing a second training operation on the first rank by executing the training code loaded to the second rank: and
storing results of performing the first and second training operations on the first and second ranks in a storage device,
wherein the results of performing the first and second training operations comprise a first reference voltage for sampling output data of the first rank, and a second reference voltage for sampling output data of the second rank.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first rank and the second rank are connected to a same memory channel.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
setting a memory controller that controls the memory device to alternately generate the first reference voltage and the second reference voltage based on a rank interleaving period.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
resuming the rank interleaving mode of the memory device.

### Claim 15 (depends on 11)

The method of claim 11, wherein the results stored in the storage device are read in a booting operation of the electronic device and are used to initialize the memory device.

### Claim 16

An electronic device, comprising:
a memory device comprising a plurality of ranks, wherein the memory device is accessed based on a rank interleaving mode; and
a system-on-chip that performs a training operation on the memory device, wherein the system-on-chip comprises:
a plurality of reference voltage generators that generates a plurality of reference voltages for sampling output data of the plurality of ranks independently of each other.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the system-on-chip sets voltage levels of the reference voltages respectively generated by the plurality of reference voltage generators through the training operation.

### Claim 18 (depends on 16)

The electronic device of claim 16, wherein the system-on-chip disables the rank interleaving mode to perform the training operation.

### Claim 19 (depends on 16)

The electronic device of claim 16, further comprising:
a storage device that stores a result of performing the training operation,
wherein the system-on-chip uses values of the plurality of reference voltage generators stored in the storage device to initialize the memory device upon booting.

### Claim 20 (depends on 16)

The electronic device of claim 16, wherein the plurality of ranks is connected to a same channel,
wherein the system-on-chip samples data transferred through the same channel from the memory device using a selected reference voltage from among the plurality of reference voltages,
wherein the selected reference voltage is generated by switching outputs of the plurality of reference voltage generators based on a rank interleaving period.

### Claim at position 21

21-24. (canceled)