# US 2019/0172408 A1 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172408 A1 - Document ID: US20190172408A1 - Status: Published application - Kind: A1 - Application number: 16/190,205 - Filed: 2018-11-14 - Published: 2019-06-06 - Earliest claimed: 2013-09-12 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Hiroyuki MIYAKE - Web page: https://patentgrep.com/patent/US20190172408A1 ## CPC - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G02F 1/134336: {Matrix} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling - G09G 2320/0223: Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes - G09G 2330/021: Power management, e.g. power saving - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times. ## Claims ### Claim 1 (canceled) ### Claim 2 A display device comprising: a first scan line supplied with only a first selection signal and a first non-selection signal; a second scan line supplied with only a second selection signal and a second non-selection signal; a first transistor; a second transistor; a first scan line driver circuit; a second scan line driver circuit; and a pixel portion between the first scan line driver circuit and the second scan line driver circuit, wherein one of a source and a drain of the first transistor is electrically connected to one end of the first scan line, wherein one of a source and a drain of the second transistor is electrically connected to one end of the second scan line, wherein the first scan line driver circuit is electrically connected to the other end of the first scan line, wherein the second scan line driver circuit is electrically connected to the other end of the second scan line, wherein the first scan line is configured such that the first selection signal is not supplied from the one end of the first scan line, and wherein the second scan line is configured such that the second selection signal is not supplied from the one end of the second scan line. ### Claim 3 (depends on 2) The display device according to claim 2, wherein each of the first transistor and the second transistor comprises an oxide semiconductor film comprising a channel formation region. ### Claim 4 (depends on 2) The display device according to claim 2, wherein a gate of the first transistor is electrically connected to the second scan line driver circuit, and wherein a gate of the second transistor is electrically connected to the first scan line driver circuit. ### Claim 5 (depends on 2) The display device according to claim 2, wherein the first transistor is controlled by a first clock signal, and wherein the second transistor is controlled by a second clock signal. ### Claim 6 A display device comprising: a first scan line supplied with a first selection signal and a first non-selection signal; a second scan line supplied with a second selection signal and a second non-selection signal; a first transistor configured to supply the first non-selection signal to the first scan line from one end of the first scan line; a second transistor configured to supply the second non-selection signal to the second scan line from one end of the second scan line; a first scan line driver circuit configured to supply the first selection signal and the first non-selection signal to the first scan line from the other end of the first scan line; a second scan line driver circuit configured to supply the second selection signal and the second non-selection signal to the second scan line from the other end of the second scan line; and a pixel portion between the first scan line driver circuit and the second scan line driver circuit, wherein the first scan line is configured such that the first selection signal is not supplied from the one end of the first scan line, and wherein the second scan line is configured such that the second selection signal is not supplied from the one end of the second scan line. ### Claim 7 (depends on 6) The display device according to claim 6, wherein each of the first transistor and the second transistor comprises an oxide semiconductor film comprising a channel formation region. ### Claim 8 (depends on 6) The display device according to claim 6, wherein a gate of the first transistor is electrically connected to the second scan line driver circuit, and wherein a gate of the second transistor is electrically connected to the first scan line driver circuit. ### Claim 9 (depends on 6) The display device according to claim 6, wherein the first transistor is controlled by a first clock signal, and wherein the second transistor is controlled by a second clock signal. ### Claim 10 A display device comprising: a first scan line supplied with a first selection signal and a first non-selection signal; a second scan line supplied with a second selection signal and a second non-selection signal; a first transistor configured to supply the first non-selection signal to the first scan line from one end of the first scan line; a second transistor configured to supply the second non-selection signal to the second scan line from one end of the second scan line; a first scan line driver circuit comprising: a third transistor configured to supply the first selection signal to the first scan line from the other end of the first scan line; and a fourth transistor configured to supply the first non-selection signal to the first scan line from the other end of the first scan line; a second scan line driver circuit; a fifth transistor configured to supply the second selection signal to the second scan line from the other end of the second scan line; and a sixth transistor configured to supply the second non-selection signal to the second scan line from the other end of the second scan line; and a pixel portion between the first scan line driver circuit and the second scan line driver circuit, wherein the first scan line is configured such that the first selection signal is not supplied from the one end of the first scan line, and wherein the second scan line is configured such that the second selection signal is not supplied from the one end of the second scan line. ### Claim 11 (depends on 10) The display device according to claim 10, wherein each of the first transistor and the second transistor comprises an oxide semiconductor film comprising a channel formation region. ### Claim 12 (depends on 10) The display device according to claim 10, wherein a gate of the first transistor is electrically connected to the second scan line driver circuit, and wherein a gate of the second transistor is electrically connected to the first scan line driver circuit. ### Claim 13 (depends on 10) The display device according to claim 10, wherein the first transistor is controlled by a first clock signal, and wherein the second transistor is controlled by a second clock signal.