# US 2019/0172397 A1 · Gate Driver and Display Device Including the Same

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- Number: US 2019/0172397 A1
- Document ID: US20190172397A1
- Status: Published application
- Kind: A1
- Application number: 16/034,274
- Filed: 2018-07-12
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Minho LEE; Seunghee KUK
- Web page: https://patentgrep.com/patent/US20190172397A1

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A gate driver and a display device including the same are disclosed. The gate driver includes a plurality of stages. Each stage includes a transistor T6 outputting an emission signal of a gate-on voltage to a node Na while a node Q is activated, a transistor T7 outputting the emission signal of a gate-off voltage to the node Na while a node QB is activated, a Q controller controlling a voltage of the node Q depending on a clock signal ECLK1 and a clock signal ECLK2 that are in antiphase, and a voltage of a node Q′, a QB controller controlling a voltage of the node QB depending on the clock signal ECLK1, the voltage of the node Q, and the voltage of the node Q′, and a capacitor CQ connected between an input terminal of the clock signal ECLK1 and the node Q.

## Claims

### Claim 1

A gate driver comprising:
a plurality of stages,
wherein each stage includes:
a transistor T6 configured to output an emission signal of a gate-on voltage to a node Na while a node Q is activated;
a transistor T7 configured to output the emission signal of a gate-off voltage to the node Na while a node QB is activated;
a Q controller configured to control a voltage of the node Q depending on a voltage of a node Q′ and a clock signal ECLK1 and a clock signal ECLK2 which are in antiphase;
a QB controller configured to control a voltage of the node QB depending on the clock signal ECLK1, the voltage of the node Q, and the voltage of the node Q′; and
a capacitor CQ connected between an input terminal of the clock signal ECLK1 and the node Q and having a first capacitance,
wherein a ratio of the first capacitance to a total capacitance including the first capacitance and a parasitic capacitance formed in the node Q is 50% or more.

### Claim 2 (depends on 1)

The gate driver of claim 1, wherein as the ratio of the first capacitance to the total capacitance increases while the voltage of the node Q is bootstrapped, a gate-to-source voltage of the transistor T6 increases.

### Claim 3 (depends on 2)

The gate driver of claim 2, wherein the voltage of the node Q is bootstrapped every time the clock signal ECLK1 of the gate-on voltage is input within a period in which the emission signal of the gate-on voltage is output.

### Claim 4 (depends on 1)

The gate driver of claim 1, wherein each stage further includes a Q′ controller configured to control the voltage of the node Q′ depending on the clock signal ECLK1, the clock signal ECLK2, and the voltage of the node Q.

### Claim 5 (depends on 4)

The gate driver of claim 4, wherein the QB controller includes:
a transistor T8 configured to be switched depending on the voltage of the node Q′ and apply the clock signal ECLK1 to a node Nb;
a transistor T9 configured to be switched depending on the clock signal ECLK1 and connect the node Nb to the node QB;
a transistor T5 configured to be switched depending on the voltage of the node Q and apply the gate-off voltage to the node QB; and
a capacitor CQB connected between the node QB and an input terminal of the gate-off voltage.

### Claim 6 (depends on 5)

The gate driver of claim 5, wherein the Q′ controller includes:
a transistor T10 configured to be switched depending on the voltage of the node Q and apply the clock signal ECLK2 to the node Q′;
a transistor T4 configured to be switched depending on the clock signal ECLK2 and apply the gate-on voltage to the node Q′; and
a capacitor CQ′ connected between the node Q′ and the node Nb.

### Claim 7 (depends on 1)

The gate driver of claim 1, wherein each stage further includes a transistor TBv including one electrode connected to the node Q and a gate electrode connected to an input terminal of the gate-on voltage,
wherein the transistor TBv is turned off while the voltage of the node Q is bootstrapped.

### Claim 8 (depends on 7)

The gate driver of claim 7, wherein the voltage of the node Q is bootstrapped every time the clock signal ECLK1 of the gate-on voltage is input within a period in which the emission signal of the gate-on voltage is output.

### Claim 9 (depends on 1)

The gate driver of claim 1, wherein each stage further includes:
a transistor T7a connected to one electrode of the transistor T7 and an input terminal of the gate-off voltage and configured to be switched depending on the voltage of the node QB; and
a transistor T11 connected to a node Nc between the transistor T7 and the transistor T7a and an input terminal of the gate-on voltage and configured to be switched depending on a voltage of the node Na.

### Claim 10 (depends on 1)

The gate driver of claim 1, wherein the Q controller includes:
a transistor T1 configured to be switched depending on the clock signal ECLK2 and apply a start signal to the node Q;
a transistor T2 configured to be switched depending on the clock signal ECLK1, of which one electrode is connected to the node Q; and
a transistor T3 configured to be switched depending on the voltage of the node Q′ and apply the gate-off voltage to the other electrode of the transistor T2.

### Claim 11 (depends on 1)

A display device comprising:
a display panel including gate lines connected to pixels; and
a gate driver according to claim 1, configured to generate an emission signal and supply the emission signal to the gate lines through stages.

### Claim 12 (depends on 11)

The display device of claim 11, wherein each pixel includes:
an organic light emitting diode (OLED);
a driving thin film transistor (TFT) configured to control a driving current flowing in the OLED depending on a gate-to-source voltage of the driving TFT; and
an emission TFT configured to be turned on or off in response to the emission signal and determine an emission timing of the OLED.