# US 2019/0171973 A1 · Automatic design flow from schematic to layout for superconducting multi-qubit systems

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- Number: US 2019/0171973 A1
- Document ID: US20190171973A1
- Status: Published application
- Kind: A1
- Application number: 15/828,613
- Filed: 2017-12-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Dongbing Shao; Markus Brink; Salvatore B. Olivadese; Jerry M. Chow
- Web page: https://patentgrep.com/patent/US20190171973A1

## CPC

- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- G06F 30/30: Circuit design
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10N 60/0912: {of Josephson-effect devices}
- H10N 60/805: {for Josephson-effect devices}
- G06F 2111/12: Symbolic schematics
- H10N 60/12: Josephson-effect devices
- H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Generating a layout for a multi-qubit chip is provided. A schematic is received as input. The schematic input includes a plurality of qubits, a plurality of coupling busses, a bus design parameter specifying a bus frequency, a plurality of readout busses, and a plurality of readout ports. A qubit design is selected from a qubit library, based on the qubit style in the schematic input. A bus style is selected from a bus information library, based on the bus style in the schematic input. A qubit layout is automatically generated by assembling the selected bus style/, selected qubit design, the plurality of readout busses and the plurality of readout ports.

## Claims

### Claim 1

A method of generating a layout for a multi-qubit chip, the method comprising:
receiving a schematic input, wherein the schematic input includes a bus design parameter specifying a bus frequency, a plurality of qubits, a plurality of coupling busses, a plurality of readout busses, and a plurality of readout ports;
selecting a qubit design from a qubit library, based on the qubit style in the schematic input;
selecting a bus style from a bus information library, based on the bus style in the schematic input;
automatically generating the plurality of coupling busses and the plurality of readout busses, based on the specified bus frequency and selected bus style; and
automatically generating a qubit layout by assembling the selected bus style, selected qubit design, the plurality of readout busses and the plurality of readout ports.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
performing a first assembly from the selected qubit design and the selected bus style, wherein a coupling bus is generated from the selected bus style and specified bus frequency, the coupling bus connects two or more qubits, and the coupling bus has a length based on the selected bus style and the specified bus frequency; and
saving an output of the first assembly.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
recognizing a failure when the generated coupling bus is longer than space available for placement; and
automatically adjusting the first assembly, wherein the adjusting includes altering a placement of one or more qubits and/or other generated coupling busses until the generated coupling bus fits in the space available for placement.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
performing a second assembly, wherein a plurality of readout busses, and a plurality of readout ports are generated and added to an output of a first assembly; and
saving an output of the second assembly.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
recognizing a failure when the generated readout bus is longer than space available for placement; and
automatically adjusting the second assembly, wherein the adjusting includes altering a placement of one or more qubits, one or more generated coupling busses, and one or more other generated readout busses until the generated readout bus fits in the space available for placement.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
recognizing and extracting repeating patterns of qubits and connection to the qubits, wherein the extracted repeating patterns are rotated, mirrored, and replicated to create a multi-qubit chip floor plan.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
combining an output of a first assembly and an output of a second assembly as the generated a qubit layout.

### Claim 8

A system for generating a layout for a multi-qubit chip, the system comprising:
a computer processor, a computer-readable storage medium, and program instructions stored on the computer-readable storage medium being executable by the processor, to cause the computer system to perform a method, comprising:
receiving a schematic input, wherein the schematic input includes a bus design parameter specifying a bus frequency, a plurality of qubits, a plurality of coupling busses, a plurality of readout busses, and a plurality of readout ports;
selecting a qubit design from a qubit library, based on the qubit style in the schematic input;
selecting a bus style from a bus information library, based on the bus style in the schematic input;
automatically generating the plurality of coupling busses and the plurality of readout busses, based on the specified bus frequency and selected bus style; and
automatically generating a qubit layout by assembling the selected bus style, selected qubit design, the plurality of readout busses and the plurality of readout ports.

### Claim 9 (depends on 8)

The system of claim 8, further comprising:
performing a first assembly from the selected qubit design and the selected bus style, wherein a coupling bus is generated from the selected bus style and the specified bus frequency, the coupling bus connects two or more qubits, and the coupling bus has a length based on the selected bus style and the specified bus frequency; and
saving an output of the first assembly.

### Claim 10 (depends on 9)

The system of claim 9, further comprising:
recognizing a failure when the generated coupling bus is longer than space available for placement; and
automatically adjusting the first assembly, wherein the adjusting includes altering a placement of one or more qubits and/or other generated coupling busses until the generated coupling bus fits in the space available for placement.

### Claim 11 (depends on 8)

The system of claim 8, further comprising
performing a second assembly, wherein a plurality of readout busses, and a plurality of readout ports are generated and added to an output of a first assembly; and
saving an output of the second assembly.

### Claim 12 (depends on 11)

The system of claim 11, further comprising:
recognizing a failure when the generated readout bus is longer than space available for placement; and
automatically adjusting the second assembly, wherein the adjusting includes altering a placement of one or more qubits, one or more generated coupling busses, and one or more other generated readout busses until the generated readout bus fits in the space available for placement.

### Claim 13 (depends on 11)

The system of claim 11, further comprising:
combining an output of a first assembly and an output of a second assembly as the generated a qubit layout.

### Claim 14

A computer program product for generating a layout for a multi-qubit chip, the computer program product comprising a computer readable tangible storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method, comprising:
receiving a schematic input, wherein the schematic input includes a plurality of qubits, a plurality of coupling busses, a plurality of readout busses, and a plurality of readout ports;
selecting a qubit design from a qubit library, based on the qubit style in the schematic input;
selecting a bus style/frequency from a bus information library, based on the bus style/frequency in the schematic input; and
automatically generating a qubit layout by assembling the selected bus style/frequency, selected qubit design, the plurality of readout busses and the plurality of readout ports.

### Claim 15 (depends on 14)

The computer program product of claim 14, further comprising:
performing a first assembly from the selected qubit design and the selected bus style/frequency, wherein a coupling bus is generated from the selected bus style/frequency, the coupling bus connects two or more qubits, and the coupling bus has a length based on the selected bus style/frequency; and
saving an output of the first assembly.

### Claim 16 (depends on 15)

The computer program product of claim 15, further comprising:
recognizing a failure when the generated coupling bus is longer than space available for placement; and
automatically adjusting the first assembly, wherein the adjusting includes altering a placement of one or more qubits and/or other generated coupling busses until the generated coupling bus fits in the space available for placement.

### Claim 17 (depends on 14)

The computer program product of claim 14 further comprising:
performing a second assembly, wherein a plurality of readout busses, and a plurality of readout ports are generated and added to an output of a first assembly; and
saving an output of the second assembly.

### Claim 18 (depends on 17)

The computer program product of claim 17, further comprising:
recognizing a failure when the generated readout bus is longer than space available for placement; and
automatically adjusting the second assembly, wherein the adjusting includes altering a placement of one or more qubits, one or more generated coupling busses, and one or more other generated readout busses until the generated readout bus fits in the space available for placement.

### Claim 19 (depends on 14)

The computer program product of claim 14, further comprising:
recognizing and extracting repeating patterns of qubits and connection to the qubits, wherein the extracted repeating patterns are rotated, mirrored, and replicated to create a multi-qubit chip floor plan.

### Claim 20 (depends on 14)

The computer program product of claim 14, further comprising:
combining an output of a first assembly and an output of a second assembly as the generated a qubit layout.