# US 2019/0171931 A1 · Systems and methods for machine learning processor with intra-die and inter-die wireless communication

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- Number: US 2019/0171931 A1
- Document ID: US20190171931A1
- Status: Published application
- Kind: A1
- Application number: 16/206,741
- Filed: 2018-11-30
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Vathys, Inc.
- Applicants: Vathys, Inc.
- Inventors: Tapabrata GHOSH
- Web page: https://patentgrep.com/patent/US20190171931A1

## CPC

- G06N 3/063: using electronic means
- G06N 20/00: Machine learning
- H04B 5/22: Capacitive coupling
- H04B 5/26: using coils
- H04B 5/266: {One coil at each side, e.g. with primary and secondary coils}
- H04B 5/72: for local intradevice communication
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 90/00: Package configurations
- G06F 17/13: Differential equations (using digital differential analysers G06F7/64)
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 44/223: {Differential pair signal lines}
- H10W 44/248: {for antennas}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H04B: TRANSMISSION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The need for specialized machine learning processors has become a major focal point in the industry as the computation demanded by machine learning workloads grows rapidly. However, the industry has quickly come to a roadblock as the industry realizes, in the context of machine learning, the device memory is more important than complex computation ability. As a result, there has been renewed interest in three dimensional and “2.5D” machine learning processors, which are more suited to handle large volume of data. However, conventional multi-layer devices use through silicon vias (TSVs) which have a number of disadvantages and drawbacks. To address these issues, method and devices are disclosed that allow wireless communication between processing layers in a 3D and/or 2.5D integrated dice machine learning processors.

## Claims

### Claim 1

A machine learning processor optimized for carrying out machine learning operations, the processor comprising:
a substrate;
a plurality of processing dice on the substrate, wherein one or more of the plurality of the processing dice are substantially vertically stacked on one another and on the substrate and the processing dice comprise circuitry to carry out machine learning operations and one or more machine learning operations is carried out with circuitry on or embedded in two or more of the plurality of processing dice; and
one or more wireless communication components embedded in and/or on one or more of the substrate and the plurality of processing dice, wherein the wireless communication components carry wireless communication signals between one or more of the substrate and the plurality of processing dice and the circuitry therein and wherein the operations of the machine learning processor comprises the communication signals.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the one or more wireless communication components comprise components providing electromagnetic coupling between the components.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the electromagnetic coupling comprises one or more of capacitive coupling and inductive coupling.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the electromagnetic coupling comprises capacitive coupling and metal layers in the plurality of dice and/or substrate form the capacitive coupling between the plurality of dice and/or the substrate.

### Claim 5 (depends on 3)

The processor of claim 3, wherein the electromagnetic coupling comprises capacitive coupling, and wherein a transistor gate in a processing die is used to form a parallel plate of a capacitive coupling.

### Claim 6 (depends on 3)

The processor of claim 3, wherein the electromagnetic coupling comprises inductive coupling and metal layers in a processing die are arranged in substantially polygonic shape to form an inductor coil.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the wireless communication components carry wireless communication signals between one or more regions of one or more of the substrate and the plurality of dice.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the one or more wireless communication components comprise components providing communication via electromagnetic radiation.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the wireless communication components comprise an antenna and/or an antenna array.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the wireless communication components comprise components providing wireless communication via one or more of capacitive coupling, inductive coupling and electromagnetic radiation.

### Claim 11 (depends on 1)

The processor of claim 1, wherein the communication signals are generated via a communication protocol.

### Claim 12 (depends on 11)

The processor of claim 11, wherein the communication protocol comprises differential signaling.

### Claim 13 (depends on 12)

The processor of claim 12, wherein differential signaling comprises one or more of Chordal coding, PAM-X, CNRZ-5, CNRZ-X, permutation vectors, vector coding, and line coding.

### Claim 14

A method of manufacturing a machine learning processor, comprising:
vertically stacking a plurality of processing dice, wherein each die comprises circuitry configured to carry out machine learning processes; and
forming a wireless communication link between processing dice, wherein the circuitry in two or more processing dice are configured to carry out machine learning processes via the wireless communication link.

### Claim 15 (depends on 14)

The method of claim 14, wherein the wireless communication link comprises one or more of capacitive coupling, inductive coupling and electromagnetic radiation.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the wireless communication link comprises: forming metal layers in the plurality of processing dice to generate parallel plate capacitors between the plurality of processing dice.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the wireless communication link comprises: using transistor gates in the plurality of processing dice to form parallel plate capacitors between the plurality of processing dice.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the wireless communication link comprises arranging metal layers in the plurality of processing dice in substantially polygonic shape to form inductor coils.

### Claim 19

A machine learning processor comprising:
a plurality of vertically stacked processing dice comprising circuitry to carry out machine learning operations;
wireless communication means embedded in two or more of the plurality of processing dice and configured to carry wireless communication signals between one or more of the plurality of processing dice and the circuitry therein and wherein the machine learning operations comprise the communication signals.

### Claim 20 (depends on 19)

The machine learning processor of claim 19 wherein the wireless communication means comprises one or more of electromagnetic coupling means and electromagnetic radiation means.