# US 2019/0171815 A1 · Multi-Level Distributed Pattern Processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171815 A1 - Document ID: US20190171815A1 - Status: Published application - Kind: A1 - Application number: 16/258,666 - Filed: 2019-01-27 - Published: 2019-06-06 - Earliest claimed: 2016-03-07 - Assignees: HangZhou HaiCun Information Technology Co., Ltd. - Inventors: Guobiao ZHANG - Web page: https://patentgrep.com/patent/US20190171815A1 ## CPC - G06F 21/564: {by virus signature recognition} - G06V 10/70: using pattern recognition or machine learning (optical pattern recognition or electronic computations therefor G06V10/88) - G06V 10/955: {using specific electronic processors} - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores - G11C 17/10: in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM - G11C 17/14: in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM - G11C 17/143: {using laser-fusible links} - G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)} - G11C 2213/71: Three dimensional array - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A multi-level distributed pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a non-volatile memory (NVM) array and a pattern-processing circuit. The NVM array and the pattern-processing circuit are disposed on different physical levels. ## Claims ### Claim 1 A pattern processor, comprising an input bus for transferring at least first data related to a first pattern; and, a plurality of storage-processing units (SPU's) communicatively coupled with said input bus, each of said SPUs comprising: at least a non-volatile memory (NVM) array for storing at least second data related to a second pattern, wherein said NVM array is not a random-access memory (RAM); a pattern-processing circuit for performing pattern processing for said first and second patterns; and inter-level connections for communicatively coupling said NVM array and said pattern-processing circuit; wherein said NVM array and said pattern-processing circuit are disposed on different physical levels. ### Claim 2 (depends on 1) The pattern processor according to claim 1, wherein said NVM array and said pattern-processing circuit at least partially overlap. ### Claim 3 (depends on 1) The pattern processor according to claim 1 being a big-data processor, wherein: said first pattern on said input bus includes at least a keyword or a regular expression; said second pattern in said NVM array includes at least a portion of big data; said pattern-processing circuit searches said portion of big data for said keyword or said regular expression. ### Claim 4 (depends on 1) The pattern processor according to claim 1 being a big-data processor, wherein: said first pattern on said input bus includes at least a portion of big data; said second pattern in said NVM array includes at least a keyword or a regular expression; said pattern-processing circuit searches said portion of big data for said keyword or said regular expression. ### Claim 5 (depends on 1) The pattern processor according to claim 1 being an anti-malware processor, wherein: said first pattern on said input bus includes at least a virus signature or a network rule; said second pattern in said NVM array includes at least a portion of user data; said pattern-processing circuit searches said portion of user data for said virus signature or said network rule. ### Claim 6 (depends on 1) The pattern processor according to claim 1 being an anti-malware processor, wherein: said first pattern on said input bus includes at least a network packet or at least a portion of user data; said second pattern in said NVM array includes at least a virus signature or a network rule; said pattern-processing circuit searches said network packet or said user data for said virus signature or said network rule. ### Claim 7 (depends on 1) The pattern processor according to claim 1 being a voice-recognition processor, wherein: said first pattern on said input bus includes at least an acoustic model or a language model; said second pattern in said NVM array includes at least a portion of voice data; said pattern-processing circuit performs pattern recognition for said voice data using said acoustic model or said language model. ### Claim 8 (depends on 1) The pattern processor according to claim 1 being a voice-recognition processor, wherein: said first pattern on said input bus includes at least a voice data; said second pattern in said NVM array includes at least an acoustic model or a language model; said pattern-processing circuit performs pattern recognition for said voice data using said acoustic model or said language model. ### Claim 9 (depends on 1) The pattern processor according to claim 1 being an image-recognition processor, wherein: said first pattern on said input bus includes at least an image model; said second pattern in said NVM array includes at least a portion of image data; said pattern-processing circuit performs pattern recognition for said image data using said image model. ### Claim 10 (depends on 1) The pattern processor according to claim 1 being an image-recognition processor, wherein: said first pattern on said input bus includes at least an image data; said second pattern in said NVM array includes at least an image model; said pattern-processing circuit performs pattern recognition for said image data using said image model. ### Claim 11 A pattern processor, comprising an input bus for transferring at least first data related to a search pattern; and, a plurality of storage-processing units (SPU) communicatively coupled with said input bus, each of said SPUs comprising: at least a non-volatile memory (NVM) array for storing at least second data related to a target pattern, wherein said NVM array is not a random-access memory; a pattern-processing circuit for performing pattern processing for said search and target patterns; and electrical connections for communicatively coupling said NVM array and said pattern-processing circuit. ### Claim 12 (depends on 11) The pattern processor according to claim 11, wherein said NVM array and said pattern-processing circuit are disposed on different physical levels. ### Claim 13 (depends on 12) The pattern processor according to claim 12, wherein said NVM array and said pattern-processing circuit at least partially overlap. ### Claim 14 (depends on 12) The pattern processor according to claim 12, wherein said NVM array and said pattern-processing circuit are monolithically integrated. ### Claim 15 (depends on 14) The pattern processor according to claim 14, wherein said NVM array is a three-dimensional memory (3D-M) array. ### Claim 16 (depends on 14) The pattern processor according to claim 14, wherein electrical connections are contact vias. ### Claim 17 (depends on 11) The pattern processor according to claim 11 being a big-data processor, wherein: said search pattern on said input bus includes at least a keyword or a regular expression; said target pattern in said NVM array includes at least a portion of big data; said pattern-processing circuit searches said portion of big data for said keyword or said regular expression. ### Claim 18 (depends on 11) The pattern processor according to claim 11 being an anti-malware processor, wherein: said search pattern on said input bus includes at least a virus signature or a network rule; said target pattern in said NVM array includes at least a portion of user data; said pattern-processing circuit searches said portion of user data for said virus signature or said network rule. ### Claim 19 (depends on 11) The pattern processor according to claim 11 being a voice-recognition processor, wherein: said search pattern on said input bus includes at least an acoustic model or a language model; said target pattern in said NVM array includes at least a portion of voice data; said pattern-processing circuit performs pattern recognition for said voice data using said acoustic model or said language model. ### Claim 20 (depends on 11) The pattern processor according to claim 11 being an image-recognition processor, wherein: said search pattern on said input bus includes at least an image model; said target pattern in said NVM array includes at least a portion of image data; said pattern-processing circuit performs pattern recognition for said image data using said image model.