# US 2019/0171783 A1 · Systems and methods for top level integrated circuit design

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- Number: US 2019/0171783 A1
- Document ID: US20190171783A1
- Status: Published application
- Kind: A1
- Application number: 15/829,216
- Filed: 2017-12-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Mellanox Technologies, Ltd.
- Applicants: Mellanox Technologies Ltd.
- Inventors: Alexander Martfeld
- Web page: https://patentgrep.com/patent/US20190171783A1

## CPC

- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/30: Circuit design
- G06F 30/36: Circuit design at the analogue level
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 2111/04: Constraint-based CAD
- G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
- G06F 2115/06: Structured ASICs
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and systems for designing an integrated circuit device are described. The method includes receiving RTL descriptions of the whole device and generating lower level component descriptions. The method further includes grouping the component descriptions into blocks, analyzing the component descriptions, and identifying block internal removable components based on the analysis. The method further includes removing the removable components. Reduced design is converted into gate-level descriptions. Finally, the method includes executing high quality and high efficiency device TOP level physical implementation and generation of physical and timing constrains for block level design.

## Claims

### Claim 1

A top level integrated circuit design method, comprising:
receiving register transfer level (RTL) descriptions of an integrated circuit device;
generating generic physical descriptions of components and connectivity, based on the RTL descriptions;
grouping the component descriptions into blocks;
analyzing the connectivity of the components descriptions;
based on the analysis, identifying components in the blocks, which can be removed with no effect on TOP level design;
removing RTL descriptions of the removable components from the blocks;
converting RTL descriptions remaining after the removal into gate level descriptions by synthesis process; and
specifying placement regions and routing blockages.

### Claim 2 (depends on 1)

The method of claim 1, further comprising updating input and output constraints of the blocks.

### Claim 3 (depends on 1)

The method of claim 1, further comprising specifying definition of block place and route area, based on placement regions and routing blockages.

### Claim 4 (depends on 1)

The method of claim 1, further comprising generating a code for specifying block pins.

### Claim 5 (depends on 1)

The method of claim 1, further comprising storing block boundary logic information in a memory device.

### Claim 6 (depends on 1)

The design method of claim 1, further comprising generating signal information by a processing unit.

### Claim 7 (depends on 1)

The method of claim 1, further comprising adding interconnects to connect the placed components, while complying with all design rules.

### Claim 8

A non-transitory computer-readable medium storing instructions which, when executed, causing one or more processors to perform a computerized method for designing top level integrated circuits, the method comprising:
receiving register transfer level (RTL) descriptions of an integrated circuit device;
generating generic physical descriptions of components and connectivity, based on the RTL descriptions;
grouping the component descriptions into blocks;
analyzing the connectivity of the components descriptions;
based on the analysis, identifying components in the blocks, which can be removed with no effect on TOP level design;
removing RTL descriptions of the removable components from the blocks;
converting RTL descriptions remaining after the removal into gate level descriptions by synthesis process; and
specifying placement regions and routing blockages.

### Claim 9

A system for IC Top level physical design, comprising:
a memory device;
an input unit;
an output unit; and
a processing unit, executing the instructions to:
receive register transfer level (RTL) descriptions of an integrated circuit device;
generate generic physical descriptions of components and connectivity, based on the RTL descriptions;
group the component descriptions into blocks;
analyze the connectivity of the components descriptions;
based on the analysis, identify components in the blocks, which can be removed with no effect on TOP level design;
remove RTL descriptions of the removable components from the blocks;
convert RTL descriptions remaining after the removal into gate level descriptions by synthesis process; and
specify placement regions and routing blockages.