# US 2019/0171601 A1 · Mechanisms for fpga chaining and unified fpga views to composed system hosts

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- Number: US 2019/0171601 A1
- Document ID: US20190171601A1
- Status: Published application
- Kind: A1
- Application number: 15/829,937
- Filed: 2017-12-03
- Published: 2019-06-06
- Earliest claimed: 2017-12-03
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Murugasamy K. Nachimuthu; Mohan J. Kumar
- Web page: https://patentgrep.com/patent/US20190171601A1

## CPC

- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU]
- G06F 15/173: using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F 15/7867: {with reconfigurable architecture}
- G06F 2009/45579: {I/O management, e.g. providing access to device drivers or storage}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.

## Claims

### Claim 1

A computer-implemented method, comprising:
linking a plurality of Field Programmable Gate Arrays (FPGA) in communication to form a chain of FPGAs, the plurality of FPGAs including an FPGA that is coupled to a processor in a compute node, each of the plurality of FPGAs having respective a size; and
exposing the chain of FPGAs to a to a hypervisor, an operating system virtualization layer, or to an operating system hosted by the compute node as a virtual monolithic FPGA have a size that is an aggregate of the individual sizes of the FPGAs in the chain of FPGAs.

### Claim 2 (depends on 1)

The method of claim 1, wherein the chain of FPGAs includes a chaining mechanism that couples a first FPGA in a first compute node in communication with a second FPGA in a second compute node.

### Claim 3 (depends on 2)

The method of claim 2, wherein the chaining mechanism comprise a cable coupled to respective ports on the first and second FPGAs.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first and second compute nodes are installed in the same pooled compute drawer.

### Claim 5 (depends on 3)

The method of claim 3, wherein the first and second compute nodes are coupled to a backplane in the pooled compute drawer and the chaining mechanism linking the first FPGA in communication with the second FPGA includes wiring in the backplane.

### Claim 6 (depends on 3)

The method of claim 3, wherein the pooled compute drawer includes backplane wiring and each of the first FPGA and second FPGA is coupled to the backplane wiring.

### Claim 7 (depends on 2)

The method of claim 2, wherein the chain of FPGAs include a first FPGA installed in a first pooled system drawer linked in communication with a second FPGA installed in a second pooled system.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first and second pooled compute drawers are linked in communication via a fabric, and wherein the chaining mechanism coupling the first FPGA in communication with the second FPGA traverses the fabric.

### Claim 9 (depends on 1)

The method of claim 1, wherein the chain of FPGAs includes a first FPGA in a first pooled system drawer linked in communication with a second FPGA in a second pooled system drawer that is linked in communication with a third FPGA in the second pooled system drawer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second and third FPGA are linked in communication via a cable.

### Claim 11 (depends on 9)

The method of claim 9, wherein the second pooled system drawer includes a backplane to which each of the first and second FPGAs are communicatively coupled, and wherein a portion of wiring in the backplane is used to carry signals to facilitate communication between the second and third FPGAs.

### Claim 12

A method implemented by components in a plurality of pooled system drawers installed in a rack, the pooled system drawers including one or more pooled compute drawers and one or more pooled Field Programmable Gate Array (FPGA) drawers, comprising:
for each of the one or more pooled compute drawers installed in a rack,
enumerating Field Programmable Gate Array (FPGA) devices that are associated with compute nodes installed in the pooled compute drawer;
for each of the one or more pooled FPGA drawers installed in a rack,
enumerating FPGAs installed in the pooled FPGA drawer;
identifying chainable FPGAs among the FPGAs that are enumerated associated with the compute nodes installed in the one or more pooled compute drawers and the FPGAs that are enumerated for the one or more pooled FPGA drawers;
identifying intra-drawer FPGA chaining mechanisms for chaining chainable FPGAs within the one or more pooled compute drawers and the one or more pooled FPGA drawers; and
identifying inter-drawer FPGA chaining mechanisms for chaining chainable FPGAs located in separate pooled system drawers; and
composing a unified view of the FPGAs for the rack, the unified view identifying a location and at least one of a size and type of each FPGA, whether the FPGA is a chainable FPGA, and a chaining mechanism for each chainable FPGA.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
composing a compute node that is enabled to access a plurality of FPGAs that are allocated for the compute node, at least two of the plurality of FPGAs being linked in communication to form a chain of FPGAs; and
updating the unified view of the FPGAs to indicate the plurality of FPGAs are allocated to the compute node.

### Claim 14 (depends on 13)

The method of claim 13, wherein the chain of FPGAs includes a chaining mechanism that links a first FPGA in a first compute node in communication with a second FPGA in a second compute node.

### Claim 15 (depends on 14)

The method of claim 14, wherein the chaining mechanism comprise a cable coupled to respective ports on the first and second FPGAs.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first and second compute nodes are installed in the same pooled compute drawer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first and second compute nodes are coupled to a backplane in the pooled compute drawer and the chaining mechanism that links the first FPGA in communication with the second FPGA includes wiring in the backplane.

### Claim 18 (depends on 16)

The method of claim 16, wherein the pooled compute drawer includes backplane wiring and each of the first FPGA and second FPGA is coupled to the backplane wiring.

### Claim 19 (depends on 14)

The method of claim 14, wherein the chain of FPGAs include first FPGA installed in a first pooled system drawer linked in communication with a second FPGA installed in a second pooled system.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first and second pooled system drawers are linked in communication via a fabric, and wherein the chaining mechanism linking the first FPGA in communication with the second FPGA traverses the fabric.

### Claim 21 (depends on 13)

The method of claim 13, wherein the chain of FPGAs includes a first FPGA in a first pooled system drawer linked in communication with a second FPGA in a second pooled system drawer that is linked in communication with a third FPGA in the second pooled system drawer.

### Claim 22 (depends on 21)

The method of claim 21, wherein the second and third FPGA are linked in communication via a cable.

### Claim 23 (depends on 21)

The method of claim 21, wherein the second pooled system drawer includes a backplane to which each of the first and second FPGAs are communicatively coupled, and wherein a portion of wiring in the backplane is used to carry signals to facilitate communication between the second and third FPGAs.

### Claim 24 (depends on 12)

The method of claim 12, further comprising:
receiving a request from a customer to be allocated compute resources including FPGA resources for use by the customer;
composing a compute node including a plurality of FPGAs to service the request, at least two of the plurality of FPGAs being chained to form a chain of FPGAs; and
enabling the customer to use the compute node that is composed.

### Claim 25

A pooled compute drawer, configured to be installed in a rack, comprising:
a plurality of compute nodes, each compute node including,
a processor;
memory, operatively coupled to the processor; and
a Field Programmable Gate Array (FPGA) device, operatively coupled to the processor;
the pooled compute drawer further including one or more chaining mechanisms for linking FPGAs included in respective compute nodes in communication to form an FPGA chain.

### Claim 26 (depends on 25)

The pooled compute drawer of claim 25, wherein a first compute node includes a first FPGA having a first port and a second compute node includes a second FPGA having a second port, and wherein a chaining mechanism comprises a cable coupled to the first and second ports on the first and second FPGAs.

### Claim 27 (depends on 26)

The pooled compute drawer of claim 26, further comprising a backplane, wherein each of a first compute node including a first FPGA and a second compute node including a second FPGA is coupled to the backplane and a chaining mechanism that links the first FPGA in communication with the second FPGA includes wiring in the backplane.

### Claim 28 (depends on 26)

The pooled compute drawer of claim 26, further comprising a backplane including backplane wiring, wherein the pooled compute drawer includes a first compute node including a first FPGA and a second compute drawer including a second FPGA, and wherein each of the first FPGA and second FPGA are communicatively coupled to a portion of the backplane wiring, linking the first FPGA in communication with the second FPGA.