# US 2019/0171595 A1 · Bit-interleaved bi-directional transmissions on a multi-drop bus for time-critical data exchange

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0171595 A1
- Document ID: US20190171595A1
- Status: Published application
- Kind: A1
- Application number: 16/184,284
- Filed: 2018-11-08
- Published: 2019-06-06
- Earliest claimed: 2017-12-05
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Lalan Jee MISHRA; Richard Dominic WIETFELDT
- Web page: https://patentgrep.com/patent/US20190171595A1

## CPC

- G06F 13/362: with centralised access control
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 13/4291: {using a clocked protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and apparatus for optimizing bus latency using bit-interleaved bidirectional transmission on a serial bus are described. A method performed at a device coupled to a serial bus includes pairing with a second device in a transaction to be conducted over the serial bus, transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus, and receiving a second data bit transmitted by the second device on the data line in a second part of each cycle. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.

## Claims

### Claim 1

A data communication method performed at a first device coupled to a serial bus, comprising:
pairing with a second device in a transaction to be conducted over the serial bus; and
for each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus:
transmitting a first data bit to the second device over a data line of the serial bus in a first part of the each cycle; and
receiving a second data bit from the second device on the data line in a second part of the each cycle.

### Claim 2 (depends on 1)

The method of claim 1, wherein the serial bus is operated in accordance with a radio frequency front-end (RFFE) protocol or a system power management interface (SPMI) protocol.

### Claim 3 (depends on 1)

The method of claim 1, wherein pairing with the second device comprises:
transmitting a device address on the serial bus, the device address identifying the second device.

### Claim 4 (depends on 3)

The method of claim 3, wherein pairing with the second device comprises:
transmitting a sequence start condition (SSC) on the serial bus before transmitting the device address.

### Claim 5 (depends on 3)

The method of claim 3, wherein pairing with the second device comprises:
participating in bus arbitration as a slave device to obtain access to the serial bus before transmitting the device address.

### Claim 6 (depends on 3)

The method of claim 3, wherein the first device and the second device are actively paired after the device address is received by the second device.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
transmitting a command to the second device over the serial bus to identify a type of a datagram to be transmitted to the second device during the transaction.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
receiving a command transmitted by the second device over the serial bus, the command identifying a type of a datagram to be received from the second device during the transaction.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
determining that an early transition in signaling state in the clock signal has occurred while transmitting a parity bit in a first direction on the data line of the serial bus; and
receiving a plurality of data bits transmitted in a second direction after completing transmission of the parity bit in the first direction, wherein the second data bit is included in the plurality of data bits.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
causing an early transition in signaling state in the clock signal while receiving a parity bit transmitted in a first direction on the data line of the serial bus; and
transmitting a plurality of data bits in a second direction after the parity bit has been transmitted, wherein the first data bit is included in the plurality of data bits.

### Claim 11

A processor-readable storage medium having one or more instructions which, when executed by at least one processor or state machine of a processing circuit, cause the processing circuit to:
pair with a second device in a transaction to be conducted over a serial bus; and
for each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus:
transmit a first data bit to the second device over a data line of the serial bus in a first part of the each cycle; and
receive a second data bit from the second device on the data line in a second part of the each cycle.

### Claim 12 (depends on 11)

The storage medium of claim 11, wherein the serial bus is operated in accordance with a radio frequency front-end (RFFE) protocol or a system power management interface (SPMI) protocol.

### Claim 13 (depends on 11)

The storage medium of claim 11, wherein the one or more instructions further cause the processing circuit to:
transmit a device address on the serial bus, the device address identifying the second device.

### Claim 14 (depends on 13)

The storage medium of claim 13, wherein the one or more instructions further cause the processing circuit to:
transmit a sequence start condition (SSC) on the serial bus before transmitting the device address.

### Claim 15 (depends on 13)

The storage medium of claim 13, wherein the one or more instructions further cause the processing circuit to:
participate in bus arbitration as a slave device to obtain access to the serial bus before transmitting the device address.

### Claim 16 (depends on 13)

The storage medium of claim 13, wherein the processing circuit and the second device are actively paired after the device address is received by the second device.

### Claim 17 (depends on 11)

The storage medium of claim 11, wherein the one or more instructions further cause the processing circuit to:
transmit a command to the second device over the serial bus to identify a type of a datagram to be transmitted to the second device during the transaction.

### Claim 18 (depends on 11)

The storage medium of claim 11, wherein the one or more instructions further cause the processing circuit to:
receive a command transmitted by the second device over the serial bus, the command identifying a type of a datagram to be received from the second device during the transaction.

### Claim 19 (depends on 11)

The storage medium of claim 11, wherein the one or more instructions further cause the processing circuit to:
determine that an early transition in signaling state in the clock signal has occurred while transmitting a parity bit in a first direction on the data line of the serial bus; and
receive a plurality of data bits transmitted in a second direction after completing transmission of the parity bit in the first direction, wherein the second data bit is included in the plurality of data bits.

### Claim 20 (depends on 11)

The storage medium of claim 11, wherein the one or more instructions further cause the processing circuit to:
cause an early transition in signaling state in the clock signal while receiving a parity bit transmitted in a first direction on the data line of the serial bus; and
transmit a plurality of data bits in a second direction after the parity bit has been transmitted, wherein the first data bit is included in the plurality of data bits.

### Claim 21

An apparatus operable to communicate data over a serial bus, comprising:
a transceiver configured to couple the apparatus to the serial bus; and
a processor coupled to the transceiver and configured to:
pair the apparatus with a second device in a transaction to be conducted over the serial bus; and
use the transceiver to exchange data with the second device by:
transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus; and
receiving a second data bit from the second device on the data line in a second part of the each cycle.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the serial bus is operated in accordance with a radio frequency front-end (RFFE) protocol or a system power management interface (SPMI) protocol.

### Claim 23 (depends on 21)

The apparatus of claim 21, wherein the processor is configured to pair the apparatus with the second device by transmitting a device address on the serial bus, the device address identifying the second device.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the processor is configured to pair the apparatus with the second device by transmitting a sequence start condition (SSC) on the serial bus before transmitting the device address.

### Claim 25 (depends on 23)

The apparatus of claim 23, wherein the processor is configured to pair the apparatus with the second device by participating in bus arbitration as a slave device to obtain access to the serial bus before transmitting the device address.

### Claim 26 (depends on 23)

The apparatus of claim 23, wherein the apparatus and the second device are actively paired after the device address is received by the second device.

### Claim 27 (depends on 21)

The apparatus of claim 21, wherein the processor is further configured to:
use the transceiver to transmit a command to the second device over the serial bus to identify a type of a datagram to be transmitted to the second device during the transaction.

### Claim 28 (depends on 21)

The apparatus of claim 21, wherein the processor is further configured to:
receive a command transmitted by the second device over the serial bus, the command identifying a type of a datagram to be received from the second device during the transaction.

### Claim 29 (depends on 21)

The apparatus of claim 21, wherein the processor is further configured to:
determine that an early transition in signaling state in the clock signal has occurred while transmitting a parity bit in a first direction on the data line of the serial bus; and
receive a plurality of data bits transmitted in a second direction after completing transmission of the parity bit in the first direction, wherein the second data bit is included in the plurality of data bits.

### Claim 30 (depends on 21)

The apparatus of claim 21, wherein the processor is further configured to:
cause an early transition in signaling state in the clock signal while receiving a parity bit transmitted in a first direction on the data line of the serial bus; and
transmit a plurality of data bits in a second direction after the parity bit has been transmitted, wherein the first data bit is included in the plurality of data bits.