# US 2019/0171591 A1 · Hybrid architecture for signal processing and signal processing accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171591 A1 - Document ID: US20190171591A1 - Status: Published application - Kind: A1 - Application number: 16/169,995 - Filed: 2018-10-24 - Published: 2019-06-06 - Earliest claimed: 2014-04-30 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Steven Perry - Web page: https://patentgrep.com/patent/US20190171591A1 ## CPC - G06F 13/1668: {Details of memory controller} - G06F 13/4234: {being a memory bus} - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/343: Logical level - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17736: Structural details of routing resources - H03K 19/17748: Structural details of configuration resources - H03K 19/1776: for memories - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports. ## Claims ### Claim 1 An integrated circuit system, comprising: programmable logic circuitry in a first region of the integrated circuit system; an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function; and an interconnect network that enables communication between ISA-based signal processors of the array of ISA-based signal processors. ### Claim 2 (depends on 1) The integrated circuit system of claim 1, wherein the programmable logic circuitry comprises field programmable gate array (FPGA) circuitry configured to send data to or receive data from the array of ISA-based signal processors. ### Claim 3 (depends on 1) The integrated circuit system of claim 1, wherein the array of ISA-based signal processors has vector processing functionality. ### Claim 4 (depends on 1) The integrated circuit system of claim 1, wherein the filtering function comprises digital pre-distortion (DPD) processing. ### Claim 5 (depends on 1) The integrated circuit system of claim 1, wherein the array of ISA-based signal processors comprises distributed memory, wherein each ISA-based signal processor of the array of ISA-based signal processors is associated with at least one memory block of the distributed memory. ### Claim 6 (depends on 1) The integrated circuit system of claim 1, wherein the interconnect network connects a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors. ### Claim 7 (depends on 6) The integrated circuit system of claim 6, wherein the array of ISA-based signal processors comprises at least a first row, a second row, and a third row of ISA-based signal processors, and a first column, a second column, and a third column of ISA-based signal processors. ### Claim 8 (depends on 1) The integrated circuit system of claim 1, comprising a hardened processing system that controls and monitors the array of ISA-based signal processors. ### Claim 9 (depends on 1) The integrated circuit system of claim 1, wherein an ISA-based signal processor of the array of ISA-based signal processors comprises an instruction unit, a program counter, or a combination thereof. ### Claim 10 (depends on 9) The integrated circuit system of claim 9, wherein the instruction unit stores microcode for the ISA-based signal processor. ### Claim 11 (depends on 9) The integrated circuit system of claim 9, wherein the program counter controls a sequence of processing steps in the ISA-based signal processor. ### Claim 12 An integrated circuit system, comprising: programmable logic circuitry in a first region of the integrated circuit system; an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region; and an interconnect network that communicatively connects a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors. ### Claim 13 The integrated circuit system of 12, wherein the array of ISA-based signal processors comprises at least a first row, a second row, and a third row of ISA-based signal processors, and a first column, a second column, and a third column of ISA-based signal processors. ### Claim 14 The integrated circuit system of 12, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function. ### Claim 15 The integrated circuit system of 14, wherein the filtering function comprises digital pre-distortion (DPD) processing. ### Claim 16 An integrated circuit system, comprising: programmable logic circuitry in a first region of the integrated circuit system; an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function; and a hardened processing system that controls and monitors the array of ISA-based signal processors. ### Claim 17 The integrated circuit system of 16, wherein the hardened processing system controls and monitors the array of ISA-based signal processors by updating contents of and configuring the array of ISA-based signal processors. ### Claim 18 (depends on 17) The integrated circuit system of claim 17, wherein the contents comprise coefficients for the filtering function. ### Claim 19 (depends on 16) The integrated circuit system of claim 16, wherein the filtering function comprises digital pre-distortion (DPD) processing. ### Claim 20 An integrated circuit system, comprising: field programmable gate array (FPGA) circuitry in a first region of the integrated circuit system; an array of instruction set architecture (ISA)-based signal processors in a second region of the integrated circuit different from the first region; and an interconnect network that communicatively connects a first ISA-based signal processor of the array of ISA-based signal processors directly to stream data to a second ISA-based signal processor of the array of ISA-based signal processors. ### Claim 21 (depends on 20) The integrated circuit system of claim 20, wherein the interconnect network communicatively connects the first ISA-based signal processor directly to the second ISA-based signal processor using unidirectional routing circuitry. ### Claim 22 (depends on 20) The integrated circuit system of claim 20, wherein the first ISA-based signal processor of the array of ISA-based signal processors comprises one or more output ports that stream data to the second ISA-based signal processor of the array of ISA-based signal processors. ### Claim 23 (depends on 21) The integrated circuit system of claim 21, wherein the second ISA-based signal processor of the array of ISA-based signal processors comprises one or more input ports that receive the data from the plurality of output ports. ### Claim 24 The integrated circuit system of 20, wherein the array of ISA-based signal processors is programmable to perform a filtering function. ### Claim 25 The integrated circuit system of 24, wherein the filtering function comprises digital pre-distortion (DPD) processing. ### Claim 26 A method, comprising: receiving input data at an array of instruction set architecture (ISA)-based signal processors in a first region of an integrated circuit separate from a second region comprising programmable logic circuitry of the integrated circuit, wherein the array of ISA-based signal processors is programmable to perform at least a filtering function; and routing communication between at least a portion of the array of ISA-based signal processors via an interconnect network. ### Claim 27 (depends on 26) The method of claim 26, wherein the array of ISA-based signal processors has vector processing functionality. ### Claim 28 (depends on 26) The method of claim 26, wherein routing communication between at least a portion of the array of ISA-based signal processor comprises streaming data from a first ISA-based signal processor of the array of ISA-based signal processors directly to a second ISA-based signal processor of the array of ISA-based signal processors. ### Claim 29 (depends on 26) The method of claim 26, wherein routing communication between at least a portion of the array of ISA-based signal processor comprises connecting a first ISA-based signal processor of the array of ISA-based signal processors to a second ISA-based signal processor of the array of ISA-based signal processors to skip a third ISA-based signal processor located between the first ISA-based signal processor and the second ISA-based signal processor in the array of ISA-based signal processors. ### Claim 30 (depends on 26) The method of claim 26, comprising transmitting instructions, via a hardened processing system, to the array of ISA-based signal processors to perform at least a filtering function. ### Claim 31 (depends on 26) The method of claim 26, comprising, in response to routing communication between at least the portion of the array of ISA-based signal processors, implementing the portion of the array of ISA-based signal processors as a signal processor engine. ### Claim 32 A method comprising: facilitating a first portion of a filtering function using a field-programmable gate array of an integrated circuit device; and performing a second portion of a filtering function using an array of instruction set architecture (ISA)-based signal processors of the integrated circuit device, wherein performing the second portion of the filtering function comprises: receiving, at the array of ISA-based signal processors, at least one instruction to perform the second portion of the filtering function; and generating output data based at least in part on the at least one instruction. ### Claim 33 (depends on 32) The method of claim 32, wherein the filtering function comprises a digital pre-distortion (DPD) filtering function. ### Claim 34 (depends on 32) The method of claim 32, comprising configuring one or more ISA-based signal processors of the array of ISA-based signal processors using a processing system. ### Claim 35 (depends on 32) The method of claim 32, comprising routing interconnections between the array of instruction set architecture (ISA)-based signal processors via an interconnect network of the integrated circuit device. ### Claim 36 (depends on 32) The method of claim 32, wherein facilitating a first portion of the filtering function comprises transmitting input signals from the field-programmable gate array to the ISA-based signal processors.