# US 2019/0171589 A1 · Clock line driving for single-cycle data over clock signaling and pre-emption request in a multi-drop bus

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- Number: US 2019/0171589 A1
- Document ID: US20190171589A1
- Status: Published application
- Kind: A1
- Application number: 16/167,193
- Filed: 2018-10-22
- Published: 2019-06-06
- Earliest claimed: 2017-12-05
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Lalan Jee MISHRA; Richard Dominic WIETFELDT
- Web page: https://patentgrep.com/patent/US20190171589A1

## CPC

- G06F 13/161: {with latency improvement}
- G06F 13/376: using a contention resolving method, e.g. collision detection, collision avoidance
- G06F 13/4291: {using a clocked protocol}
- G06F 2213/0008: High speed serial bus, e.g. Fiber channel
- G06F 2213/0064: Latency reduction in handling transfers
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

## Claims

### Claim 1

A method for transmitting data over a serial bus comprising:
providing a clock signal on a first line of the serial bus;
transmitting data on a second line of the serial bus in accordance with timing provided by the clock signal;
causing a driver of the first line of the serial bus to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line;
detecting a first pulse on the clock signal while the driver of the first line is in the high impedance state;
causing the driver of the first line of the serial bus to exit the high impedance state prior to transmitting a second edge in the clock signal, wherein the first edge and the second edge comprise transitions in opposite directions; and
initiating bus arbitration after detecting the first pulse.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
determining identity of a first device that transmitted the first pulse based on temporal position of the first pulse between the first edge in the clock signal and the second edge in the clock signal.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
detecting a second pulse on the clock signal while the driver of the first line is in the high impedance state; and
determining identity of a second device that transmitted the second pulse based on temporal position of the second pulse between the first edge in the clock signal and the second edge in the clock signal.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
selecting a winning device from the first device and the second device based on an outcome of the bus arbitration; and
providing the winning device with access to the serial bus.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
selecting a winning device from the first device and the second device based on an outcome of the bus arbitration; and
relinquishing ownership of the serial bus to the winning device.

### Claim 6 (depends on 2)

The method of claim 2, further comprising:
relinquishing ownership of the serial bus to the first device.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
causing the driver of the first line to enter the high impedance state after transmitting a third edge in the clock signal, the first edge and the third edge occurring in different cycles of the clock signal;
determining whether a second pulse is transmitted on the clock signal while the driver of the first line is in the high impedance state after the third edge;
initiating the bus arbitration when the first pulse is detected and the second pulse is transmitted; and
ignoring the first pulse when the second pulse is not transmitted.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
determining identity of a first device that transmitted the first pulse based on temporal position of the first pulse between the first edge in the clock signal and the second edge in the clock signal; and
initiating the bus arbitration when the second pulse is transmitted in a same temporal position relative to the third edge; and
ignoring the first pulse when the second pulse is not transmitted in the same temporal position relative to the third edge.

### Claim 9

An apparatus, comprising:
a bus interface configured to couple the apparatus to a serial bus, the bus interface including a line driver adapted to drive a first line of the serial bus; and
a controller configured to:
provide a clock signal on the first line of the serial bus;
transmit data on a second line of the serial bus in accordance with timing provided by the clock signal;
cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line;
detect a first pulse on the clock signal while the line driver is in the high impedance state;
cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, wherein the first edge and the second edge comprise transitions in opposite directions; and
initiate bus arbitration after detecting the first pulse.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the controller is further configured to:
determine identity of a first device that transmitted the first pulse based on temporal position of the first pulse between the first edge in the clock signal and the second edge in the clock signal.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the controller is further configured to:
detect a second pulse on the clock signal while the line driver of the first line is in the high impedance state; and
determine identity of a second device that transmitted the second pulse based on temporal position of the second pulse between the first edge in the clock signal and the second edge in the clock signal.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the controller is further configured to:
select a winning device from the first device and the second device based on an outcome of the bus arbitration; and
provide the winning device with access to the serial bus.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the controller is further configured to:
select a winning device from the first device and the second device based on an outcome of the bus arbitration; and
relinquish ownership of the serial bus to the winning device.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the controller is further configured to:
relinquish ownership of the serial bus to the first device.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the controller is further configured to:
cause the line driver of the first line to enter the high impedance state after transmitting a third edge in the clock signal, the first edge and the third edge occurring in different cycles of the clock signal;
determine whether a second pulse is transmitted on the clock signal while the line driver of the first line is in the high impedance state after the third edge;
initiate the bus arbitration when the second pulse is transmitted; and
ignore the first pulse when the second pulse is not transmitted.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the controller is further configured to:
determine identity of a first device that transmitted the first pulse based on temporal position of the first pulse between the first edge in the clock signal and the second edge in the clock signal;
initiate the bus arbitration when the second pulse is transmitted in a same temporal position relative to the third edge; and
ignore the first pulse when the second pulse is not transmitted in the same temporal position relative to the third edge.

### Claim 17

A processor-readable storage medium comprising code for:
providing a clock signal on a first line of a serial bus;
transmitting data on a second line of the serial bus in accordance with timing provided by the clock signal;
causing a driver of the first line of the serial bus to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line;
detecting a first pulse on the clock signal while the driver of the first line is in the high impedance state;
causing the driver of the first line of the serial bus to exit the high impedance state prior to transmitting a second edge in the clock signal, wherein the first edge and the second edge comprise transitions in opposite directions; and
initiating bus arbitration after detecting the first pulse.

### Claim 18 (depends on 17)

The processor-readable storage medium of claim 17, further comprising code for:
determining identity of a first device that transmitted the first pulse based on temporal position of the first pulse between the first edge in the clock signal and the second edge in the clock signal.

### Claim 19 (depends on 18)

The processor-readable storage medium of claim 18, further comprising code for:
detecting a second pulse on the clock signal while the driver of the first line is in the high impedance state; and
determining identity of a second device that transmitted the second pulse based on temporal position of the second pulse between the first edge in the clock signal and the second edge in the clock signal.

### Claim 20 (depends on 19)

The processor-readable storage medium of claim 19, further comprising code for:
selecting a winning device from the first device and the second device based on an outcome of the bus arbitration; and
providing the winning device with access to the serial bus.

### Claim 21 (depends on 19)

The processor-readable storage medium of claim 19, further comprising code for:
selecting a winning device from the first device and the second device based on an outcome of the bus arbitration; and
relinquishing ownership of the serial bus to the winning device.

### Claim 22 (depends on 18)

The processor-readable storage medium of claim 18, further comprising code for:
relinquishing ownership of the serial bus to the first device.

### Claim 23 (depends on 17)

The processor-readable storage medium of claim 17, further comprising code for:
causing the driver of the first line to enter the high impedance state after transmitting a third edge in the clock signal, the first edge and the third edge occurring in different cycles of the clock signal;
determining whether a second pulse is transmitted on the clock signal while the driver of the first line is in the high impedance state after the third edge;
initiating the bus arbitration when the first pulse is detected and the second pulse is transmitted; and
ignoring the first pulse when the second pulse is not transmitted.

### Claim 24 (depends on 23)

The processor-readable storage medium of claim 23, further comprising code for:
determining identity of a first device that transmitted the first pulse based on temporal position of the first pulse between the first edge in the clock signal and the second edge in the clock signal; and
initiating the bus arbitration when the second pulse is transmitted in a same temporal position relative to the third edge; and
ignoring the first pulse when the second pulse is not transmitted in the same temporal position relative to the third edge.

### Claim 25

A method for transmitting data over a serial bus comprising:
receiving a clock signal from a first line of the serial bus;
receiving data from a second line of the serial bus in accordance with timing provided by the clock signal;
transmitting a pulse on the clock signal while the clock signal is in a first signaling state; and
participating in bus arbitration after transmitting the pulse on the clock signal.

### Claim 26 (depends on 25)

The method of claim 25, further comprising:
configuring a temporal position of the pulse relative to at least one edge in the clock signal, the temporal position of the pulse identifying a source of the pulse.

### Claim 27 (depends on 26)

The method of claim 26, wherein the temporal position of the pulse is determined by configuration information.

### Claim 28 (depends on 25)

The method of claim 25, further comprising:
detecting a first edge in the clock signal; and
after detecting the first edge in the clock signal, delaying transmission of the pulse by a period of time that uniquely identifies a source of the pulse.

### Claim 29 (depends on 25)

The method of claim 25, further comprising:
acquiring control of the serial bus after winning the bus arbitration.