# US 2019/0171585 A1 · Information processing device, information processing method, and computer program product > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171585 A1 - Document ID: US20190171585A1 - Status: Published application - Kind: A1 - Application number: 15/911,328 - Filed: 2018-03-05 - Published: 2019-06-06 - Earliest claimed: 2017-12-01 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Tomoko YONEMURA; Ryuta NARA - Web page: https://patentgrep.com/patent/US20190171585A1 ## CPC - G06F 12/1483: {using an access-table, e.g. matrix or list} - G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)} - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/1475: {in a virtual system, e.g. with translation means} - G06F 13/1663: {Access to shared memory} - G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) - G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings} - G06F 2212/1016: Performance improvement - G06F 2212/1052: Security improvement - G06F 2212/656: Address space sharing - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to an embodiment, an information processing device includes a monitoring circuit, a non-secure processing circuit, a secure processing circuit, memory access control circuit. The monitoring circuit switches mode between a non-secure mode and a secure mode. The non-secure processing circuit runs in the non-secure mode, and reads communication data from and writes communication data in a shared memory. The secure processing circuit runs in the secure mode, and reads the communication data from the shared memory and writes the communication data in a storage. The memory access control circuit manages access from the non-secure processing circuit and the secure processing circuit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing circuit or indicating an unlocked state attained by cancelling the locked state. ## Claims ### Claim 1 An information processing device comprising: a monitoring circuit configured to switch mode between a non-secure mode and a secure mode; a non-secure processing circuit configured to run in the non-secure mode, and read communication data from and write communication data in a shared memory; a secure processing circuit configured to run in the secure mode, and read the communication data from the shared memory and write the communication data in a storage; and a memory access control circuit configured to manage access from the non-secure processing circuit and the secure processing circuit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing circuit or indicating an unlocked state attained by cancelling the locked state. ### Claim 2 (depends on 1) The device according to claim 1, wherein when the communication data is written in the shared memory, the non-secure processing circuit issues a first-type switching instruction to the monitoring circuit for switching mode from the non-secure mode to the secure mode, and upon receiving the first-type switching instruction, the monitoring circuit switches mode from the non-secure mode to the secure mode and updates, to the locked state, the state information that is specified in the memory access control table and that corresponds to physical addresses at which the communication data is written. ### Claim 3 (depends on 2) The device according to claim 2, wherein when a certain number of sets of the communication data are written in the shared memory, the non-secure processing circuit issues the first-type switching instruction to the monitoring circuit. ### Claim 4 (depends on 1) The device according to claim 1, wherein when a first-type switching instruction for switching mode from the non-secure mode to the secure mode is received from a timer circuit, the monitoring circuit switches mode from the non-secure mode to the secure mode and updates, to the locked state, the state information that is specified in the memory access control table and that corresponds to physical addresses at which the communication data is written, and the timer circuit issues the first-type switching instruction to the monitoring circuit after elapse of a predetermined period of time since previous instance of sending the first-type switching instruction. ### Claim 5 (depends on 1) The device according to claim 1, wherein when the communication data written in the shared memory is stored in the storage, the secure processing circuit updates, to the unlocked state, the state information that is specified in the memory access control table and that corresponds to physical addresses of the communication data stored in the storage, and then issues a second-type switching instruction to the monitoring circuit for switching mode from the secure mode to the non-secure mode, and upon receiving the second-type switching instruction, the monitoring circuit switches mode from the secure mode to the non-secure mode. ### Claim 6 (depends on 5) The device according to claim 5, wherein when a certain number of sets of the communication data are written in the shared memory, the secure processing circuit stores the communication data, which is written in the shared memory, in the storage. ### Claim 7 (depends on 1) The device according to claim 1, wherein when it is determined that there is a writing violation by the non-secure processing circuit, the memory access control circuit notifies the secure processing circuit about violation information containing physical addresses at which the violation information is determined to have occurred and containing the communication data to be written, and the secure processing circuit includes a violation instruction executing circuit that performs a violation response operation in which according to the violation information, the communication data that is already written at physical addresses specified in the violation information is made unreadable for the non-secure processing circuit, and the communication data specified in the violation information is written in the shared memory and is made readable for the non-secure processing circuit. ### Claim 8 (depends on 1) The device according to claim 1, further comprising a processor circuit configured to be selectively switched between the secure mode and the non-secure mode and perform data processing in each mode, wherein the processor circuit includes a memory managing circuit configured, when it is determined that there is a writing violation by the non-secure processing circuit, to perform a violation response operation in which the communication data that is already written at physical addresses at which the writing violation is determined to have occurred is made unreadable for the non-secure processing circuit, and the communication data that is to be written but that is determined to be involved in the writing violation is written in the shared memory and is made readable for the non-secure processing circuit. ### Claim 9 (depends on 7) The device according to claim 7, wherein in the violation response operation, the communication data that is already written at target physical addresses for writing is moved to new physical addresses different than the target physical addresses for writing, the communication data to be written is written at the target physical addresses for writing, and the memory access control table and a secure page table, which indicates association of virtual addresses used by the secure processing circuit and physical addresses, are updated according to physical addresses at which writing is performed. ### Claim 10 (depends on 8) The device according to claim 8, wherein in the violation response operation, the communication data that is already written at target physical addresses for writing is moved to new physical addresses different than the target physical addresses for writing, the communication data to be written is written at the target physical addresses for writing, and the memory access control table and a secure page table, which indicates association of virtual addresses used by the secure processing circuit and physical addresses, are updated according to physical addresses at which writing is performed. ### Claim 11 (depends on 7) The device according to claim 7, wherein in the violation response operation, the communication data to be written is written at new physical addresses different than target physical addresses for writing, and a secure page table, which indicates association of virtual addresses used by the secure processing circuit and physical addresses, and a non-secure page table, which indicates association of virtual addresses used by the non-secure processing circuit and physical addresses, are updated according to physical addresses at which writing is performed. ### Claim 12 (depends on 8) The device according to claim 8, wherein in the violation response operation, the communication data to be written is written at new physical addresses different than target physical addresses for writing, and a secure page table, which indicates association of virtual addresses used by the secure processing circuit and physical addresses, and a non-secure page table, which indicates association of virtual addresses used by the non-secure processing circuit and physical addresses, are updated according to physical addresses at which writing is performed. ### Claim 13 (depends on 1) The device according to claim 1, wherein at time of activation, the secure processing circuit or the monitoring circuit updates, to the unlocked state, all of the state information in the memory access control table. ### Claim 14 (depends on 1) The device according to claim 1, wherein at time of activation, the non-secure processing circuit and the secure processing circuit loads addresses for the shared memory in a memory circuit. ### Claim 15 (depends on 1) The device according to claim 1, wherein at time of deactivation, the secure processing circuit writes, in the storage, the communication data stored in the shared memory. ### Claim 16 An information processing method comprising: Switching, by a monitoring unit, mode between a non-secure mode and a secure mode; reading-writing, by a non-secure processing unit, that includes running in the non-secure mode, and reading communication data from and writing communication data in a shared memory; writing, by a secure processing unit, that includes running in the secure mode, and reading the communication data from the shared memory and writing the communication data in a storage; and managing, by a memory access control unit, access from the non-secure processing unit and the secure processing unit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing unit or indicating an unlocked state attained by cancelling the locked state. ### Claim 17 A computer program product having a computer readable medium including programmed instructions, wherein the instructions, when executed by a computer, cause the computer to function as: a monitoring unit configured to switch mode between a non-secure mode and a secure mode; a non-secure processing unit configured to run in the non-secure mode, and read communication data from and write communication data in a shared memory; a secure processing unit configured to run in the secure mode, and read the communication data from the shared memory and write the communication data in a storage; and a memory access control unit configured to manage access from the non-secure processing unit and the secure processing unit based on a memory access control table in which physical addresses in the shared memory are associated with state information either indicating a locked state for not allowing writing but allowing reading by the non-secure processing unit or indicating an unlocked state attained by cancelling the locked state.