# US 2019/0171574 A1 · Multi-core processor with software-hardware co-managed cache system

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0171574 A1
- Document ID: US20190171574A1
- Status: Published application
- Kind: A1
- Application number: 16/209,795
- Filed: 2018-12-04
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Beijing Panyi Technology Co., Ltd.
- Applicants: Beijing Panyi Technology Co., Ltd.
- Inventors: Xingzhi Wen
- Web page: https://patentgrep.com/patent/US20190171574A1

## CPC

- G06F 12/0815: Cache consistency protocols
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0871: Allocation or management of cache space
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 12/0888: using selective caching, e.g. bypass
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Aspects of the present disclosure describe a cache system that is co-managed by software and hardware that obviates use of a cache coherence protocol. In some embodiments, a cache would have the following two hardware interfaces that are driven by software: (1) invalidate or flush its content to the lower level memory hierarchy; (2) specify memory regions that can be cached. Software would be responsible for specifying what regions can be cacheable, and may flexibly change memory from cacheable and not, depending on the stage of the software program. In some embodiments, invalidation can be done in one cycle. Multiple valid bits can be kept for each tag in the memory. A vector “valid bit vec” comprising a plurality of bits can be used. Only one of two bits may be used as the valid bit to indicate that this region of memory is holding valid information for use by the software.

## Claims

### Claim 1

A method of a computer program for managing a cache memory executed in a computing environment, the method comprising:
specifying a first region of memory to function as a read-only region;
specifying the first region of memory to be cacheable while the first region of memory functions as a read-only region;
specifying a second region of memory to function as a read-only region;
specifying the second region of memory to be cacheable while the second region of memory functions as a read-only region;
causing a write action in the first region of memory that changes memory content of the first region of memory;
invalidating the first region of memory as cacheable upon causing the write action of the first region of memory; and
maintaining the second region of memory as cacheable while the first region is invalidated as cacheable.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
directing a first processor to perform a first write action in a third region of memory;
directing a second processor to perform a second write action in the third region of memory, wherein the first write action does not possess any dependency with the section write action necessary to perform either the first or the second write actions; and
based on not possessing any dependencies, specifying the third region of memory as a cacheable region while the first processor performs the first write action and the second processor performs the second write action.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second processor performs the second write action in parallel with the first processor performing the first write action.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first write action generates a first updated value in the third region of memory and the second write action generates a second updated value in the third region of memory, and the method further comprises:
flushing the first updated value and the second updated value to a lower level memory region before the first updated value and the second update value are used by another processor.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first region of memory comprises a plurality of writeable memory registers, and invalidating the first region of memory occurs in one operation cycle.

### Claim 6 (depends on 1)

The method of claim 1, wherein invalidating the first region of memory comprises: accessing a valid bit vector comprising at least a first bit indicating whether the first region of memory comprises valid information, and a second bit indicating whether the first region of memory is cacheable by the computer program; and
updating the second bit to indicate that the first region of memory is no longer cacheable by the computer program.

### Claim 7 (depends on 6)

The method of claim 6, further comprising initializing the first region of memory to be cacheable again by re-initializing the first bit and re-initializing the second bit.

### Claim 8

A computer apparatus comprising:
at least one processor;
a memory communicatively coupled to the at least one processor and configured to be cacheable by a software program; and
the at least one processor configured to execute instructions of the software program comprising:
specifying a first region of the memory to function as a read-only region;
specifying the first region of the memory to be cacheable while the first region of memory functions as a read-only region;
specifying a second region of the memory to function as a read-only region;
specifying the second region of the memory to be cacheable while the second region of memory functions as a read-only region;
causing a write action in the first region of the memory that changes memory content of the first region of the memory;
invalidating the first region of the memory as cacheable upon causing the write action of the first region of memory; and
maintaining the second region of the memory as cacheable while the first region is invalidated as cacheable.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the at least one processor is further configured to execute instructions by the software program further comprising:
directing a first processor to perform a first write action in a third region of the memory;
directing a second processor to perform a second write action in the third region of the memory, wherein the first write action does not possess any dependency with the section write action necessary to perform either the first or the second write actions; and
based on not possessing any dependencies, specifying the third region of the memory as a cacheable region while the first processor performs the first write action and the second processor performs the second write action.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the second processor performs the second write action in parallel with the first processor performing the first write action.

### Claim 11 (depends on 9)

The apparatus of claim 9, further comprising a lower level memory communicatively coupled to the memory and the at least one processor; and
wherein the first write action generates a first updated value in the third region of the memory and the second write action generates a second updated value in the third region of the memory, and the instructions further comprise:
flushing the first updated value and the second updated value to the lower level memory region before the first updated value and the second update value are used by another processor.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the first region of the memory comprises a plurality of writeable memory registers, and invalidating the first region of memory occurs in one operation cycle.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein invalidating the first region of the memory comprises: accessing a valid bit vector comprising at least a first bit indicating whether the first region of the memory comprises valid information, and a second bit indicating whether the first region of the memory is cacheable by the computer program; and
updating the second bit to indicate that the first region of the memory is no longer cacheable by the computer program.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the instructions further comprise initializing the first region of the memory to be cacheable again by re-initializing the first bit and re-initializing the second bit.

### Claim 15

A method of a computer program for managing validity of cache regions for a multi-core processor, the method comprising:
storing a first tag representing a first memory region and a first vector comprising at least a first bit and a second bit;
storing a second tag representing a second memory region and a second vector comprising at least a third bit and a fourth bit;
setting the first, second, third and fourth bit as zero;
storing an active bit indicator;
controlling the first bit to indicate whether the first memory region is a candidate for caching, and controlling the third bit to indicate whether the second memory region is a candidate for caching, when the active bit indicator is zero; and
controlling the second bit to indicate whether the first memory region is a candidate for caching, and controlling the fourth bit to indicate whether the second memory region is a candidate for caching, when the active bit indicator is one.