# US 2019/0171569 A1 · On-demand multi-tiered hang buster for smt microprocessor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0171569 A1
- Document ID: US20190171569A1
- Status: Published application
- Kind: A1
- Application number: 15/831,658
- Filed: 2017-12-05
- Published: 2019-06-06
- Earliest claimed: 2017-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steven J. BATTLE; Dung Q. Nguyen; Susan E. Eisen; Kenneth L. Ward; Eula Faye Abalos Tolentino; Cliff Kucharski; Glenn O. Kincaid; David S. Walder
- Web page: https://patentgrep.com/patent/US20190171569A1

## CPC

- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/524: {Deadlock detection or avoidance}
- G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0877: Cache access modes
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 2212/40: Specific encoding of data in memory or cache
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments include systems, methods, and computer program products for using a multi-tier hang buster for detecting and breaking out of hang conditions in a processor. One method includes determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor. The method also includes, after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition. The method further includes, after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.

## Claims

### Claim 1

A computer-implemented method for breaking out of a hang condition in a processor, comprising:
determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor;
after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition; and
after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, wherein detecting the hang condition comprises:
monitoring an amount of time that has elapsed since a previous completion on the first thread; and
determining that the amount of time that has elapsed since the previous completion on the first thread is above a threshold.

### Claim 3 (depends on 1)

The computer-implemented method of claim 1, wherein detecting the hang condition comprises:
monitoring a number of completions on at least a second thread in the processor; and
determining that the number of completions on the at least a second thread in the processor is above a threshold.

### Claim 4 (depends on 1)

The computer-implemented method of claim 1, wherein the one or more actions available at the one or more second tiers have a greater impact on operation of the processor than the one or more actions available at the first tier, wherein the impact on the operation of the processor comprises at least one of impact to memory, load, and speed of the processor.

### Claim 5 (depends on 1)

The computer-implemented method of claim 1, further comprising:
upon reaching a last tier of the plurality of tiers:
determining that the hang condition is still present; and
performing a flush operation to break out of the hang condition.

### Claim 6 (depends on 1)

The computer-implemented method of claim 1, further comprising:
detecting that at least one of the plurality of actions performed by the first thread impacts at least a second thread in the processor;
determining, based on one or more conditions, at least one of whether to allow subsequent actions from the at least second thread to impact the first thread and whether to allow subsequent actions from the first thread to impact the at least second thread; and
managing the subsequent actions from the first thread at the at least second thread based on the determination of whether to allow the subsequent actions.

### Claim 7 (depends on 6)

The computer-implemented method of claim 6, wherein the one or more conditions comprise at least one of whether the first thread was a last thread to request a flush, a current tier on each of the first thread and at least second thread, and whether there was a completion on the first thread or at least second thread after a flush operation.

### Claim 8

A system, comprising:
at least one processor; and
a memory storing a program, which, when executed on the at least one processor, perform an operation for breaking out of a hang condition in the processor, the operation comprising:
determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor;
after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition; and
after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.

### Claim 9 (depends on 8)

The system of claim 8, wherein detecting the hang condition comprises:
monitoring an amount of time that has elapsed since a previous completion on the first thread; and
determining that the amount of time that has elapsed since the previous completion on the first thread is above a threshold.

### Claim 10 (depends on 8)

The system of claim 8, wherein detecting the hang condition comprises:
monitoring a number of completions on at least a second thread in the processor; and
determining that the number of completions on the at least a second thread in the processor is above a threshold.

### Claim 11 (depends on 8)

The system of claim 8, wherein the one or more actions available at the one or more second tiers have a greater impact on operation of the processor than the one or more actions available at the first tier, wherein the impact on the operation of the processor comprises at least one of impact to memory, load, and speed of the processor.

### Claim 12 (depends on 8)

The system of claim 8, the operation further comprising:
upon reaching a last tier of the plurality of tiers:
determining that the hang condition is still present; and
performing a flush operation to break out of the hang condition.

### Claim 13 (depends on 8)

The system of claim 8, the operation further comprising:
detecting that at least one of the plurality of actions performed by the first thread impacts at least a second thread in the processor;
determining, based on one or more conditions, at least one of whether to allow subsequent actions from the at least second thread to impact the first thread and whether to allow subsequent actions from the first thread to impact the at least second thread; and
managing the subsequent actions from the first thread at the at least second thread based on the determination of whether to allow the subsequent actions.

### Claim 14 (depends on 13)

The system of claim 13, wherein the one or more conditions comprise at least one of whether the first thread was a last thread to request a flush, a current tier on each of the first thread and at least second thread, and whether there was a completion on the first thread or at least second thread after a flush operation.

### Claim 15

A computer program product, the computer program product comprising:
a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation for breaking out of a hang condition in a processing unit, the operation comprising:
determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processing unit;
after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition; and
after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.

### Claim 16 (depends on 15)

The computer program product of claim 15, wherein detecting the hang condition comprises:
monitoring an amount of time that has elapsed since a previous completion on the first thread; and
determining that the amount of time that has elapsed since the previous completion on the first thread is above a threshold.

### Claim 17 (depends on 15)

The computer program product of claim 15, wherein detecting the hang condition comprises:
monitoring a number of completions on at least a second thread in the processing unit; and
determining that the number of completions on the at least a second thread in the processing unit is above a threshold.

### Claim 18 (depends on 15)

The computer program product of claim 15, wherein the one or more actions available at the one or more second tiers have a greater impact on operation of the processing unit than the one or more actions available at the first tier, wherein the impact on the operation of the processing unit comprises at least one of impact to memory, load, and speed of the processing unit.

### Claim 19 (depends on 15)

The computer program product of claim 15, the operation further comprising:
detecting that at least one of the plurality of actions performed by the first thread impacts at least a second thread in the processing unit;
determining, based on one or more conditions, at least one of whether to allow subsequent actions from the at least second thread to impact the first thread and whether to allow subsequent actions from the first thread to impact the at least second thread; and
managing the subsequent actions from the first thread at the at least second thread based on the determination of whether to allow the subsequent actions.

### Claim 20 (depends on 19)

The computer program product of claim 19, wherein the one or more conditions comprise at least one of whether the first thread was a last thread to request a flush, a current tier on each of the first thread and at least second thread, and whether there was a completion on the first thread or at least second thread after a flush operation.