# US 2019/0171567 A1 · Apparatuses and methods for providing data to a configurable storage area

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- Number: US 2019/0171567 A1
- Document ID: US20190171567A1
- Status: Published application
- Kind: A1
- Application number: 16/272,945
- Filed: 2019-02-11
- Published: 2019-06-06
- Earliest claimed: 2013-08-14
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Graziano Mirichigni; Luca Porzio; Erminio Di Martino; Giacomo Bernardi; Domenico Monteleone; Stefano Zanardi; Chee Weng Tan; Sebastien LeMarie; Andre Klindworth
- Web page: https://patentgrep.com/patent/US20190171567A1

## CPC

- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 )
- G06F 13/1673: {using buffers}
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 2212/1024: Latency reduction
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus mau include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

## Claims

### Claim 1

An apparatus, comprising:
an array having a storage area;
a register configured to store at least one bit;
a buffer configured to store data; and
a memory control circuit configured to control the storage area of the array to store the data stored in the buffer based on the at least one bit stored in the register.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the at least one bit defines a partition of the array as the storage area.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the at least one bit indicates an offset for the storage area relative to a size of the array.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the at least one bit defines a partition of the array as the storage area by a size and/or offset of the storage area relative to an address of the storage area.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the memory control circuit is further configured to control the storage area of the array to store the data based on a flush command.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the memory control circuit is further configured to interrupt the flush command.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the memory control circuit is further configured to:
receive a flush command,
control the storage area of the array to store the data in response to the flush command, and
responsive to a latency period for a read command or a write command, interrupt the flush command.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the memory control circuit is further configured to receive a command among a plurality of commands,
wherein the received command is a flush command, the plurality of commands include at least one other command, and
wherein the memory control circuit is further configured to interrupt the flush command to prepare for the at least one other command.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the array comprises non-volatile memory.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the memory control circuit is further configured to access one of a random access memory and a read only memory.

### Claim 11

An apparatus, comprising:
an array;
a register configured to store at least one bit; and
a control circuit configured to:
control a partition of the array to receive data, and store the received data, and
control the partition of the array to store the received data responsive to a flush command.

### Claim 12 (depends on 11)

The apparatus of claim 11, further comprising a buffer configured to store and provide the data to the partition of the array,
wherein the partition of the array is defined based on the at least one bit stored in the register.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the at least one bit defines the partition of the array as a storage area by a size and/or offset of the storage area relative to an address of the storage area.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the array comprises non-volatile memory.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein the control circuit is further configured to interrupt the flush command.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the control circuit is further configured to access one of a random access memory and a read only memory.

### Claim 17

An apparatus, comprising:
a storage area in an array;
a buffer configured to store data; and
a memory control circuit configured to control the storage area to store the data stored in the buffer based on a flush command, responsive to a plurality of bits configured to define a partition of the array as the storage area.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the memory control circuit is further configured to interrupt the flush command to prepare for at least one other command.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the memory control circuit is further configured to access one of a random access memory and a read only memory.

### Claim 20 (depends on 17)

The apparatus of claim 17, wherein the plurality of bits define the partition of the array as the storage area by a size and/or offset of the storage area relative to an address of the storage area.

### Claim 21

A wireless device, comprising:
a storage area;
a register configured to store at least one bit;
a buffer configured to store data; and
a control circuit configured to control the storage area to receive and store the data based on the at least one bit.

### Claim 22 (depends on 21)

The wireless device of claim 21, wherein the buffer includes a plurality of cache lines configured to store the data to be provided to, and stored in, the storage area.

### Claim 23 (depends on 21)

The wireless device of claim 21, further comprising an array having the storage area,
wherein the at least one bit indicates an offset for the storage area relative to a size of the array.

### Claim 24 (depends on 21)

The wireless device of claim 21, wherein the control circuit is further configured to access one of a random access memory and a read only memory.