# US 2019/0171520 A1 · Internally-generated data storage in spare memory locations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171520 A1 - Document ID: US20190171520A1 - Status: Published application - Kind: A1 - Application number: 15/830,054 - Filed: 2017-12-04 - Published: 2019-06-06 - Earliest claimed: 2017-12-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: David D. Cadigan; Stephen Glancy; Frank LaPietra; Kevin McIlvain; Jeremy R. Neaton; Richard D. Wheeler - Web page: https://patentgrep.com/patent/US20190171520A1 ## CPC - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information. ## Claims ### Claim 1 A method comprising: generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system; storing the event-based information in a reserved portion of the first memory device; and providing the event-based information to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information. ### Claim 2 (depends on 1) The method of claim 1, further comprising: storing an interface error correcting code (ECC) for the memory row in the first memory device in combination with the event-based information, wherein the interface ECC is computed across the memory devices by the memory controller. ### Claim 3 (depends on 2) The method of claim 2, further comprising: storing an internally-generated device ECC in the first memory device and in each of the plurality of memory devices; checking the internally-generated device ECC in the first memory device and in each of the plurality of memory devices upon a read operation; and internally correcting an error detected in a value read from the first memory device or the plurality of memory devices based on the internally-generated device ECC prior to sending the value to the memory controller. ### Claim 4 (depends on 3) The method of claim 3, wherein the event-based information is updated based on an access to the internally-generated device ECC in the first memory device. ### Claim 5 (depends on 2) The method of claim 2, wherein the plurality of memory devices store data, and the event-based information is transferred across a plurality of beats of a multi-beat burst to the memory controller including data from the memory row and the interface ECC. ### Claim 6 (depends on 2) The method of claim 2, further comprising: dynamically remapping an interface of the first memory device to switch between outputting the interface ECC and the event-based information on a bit line of the first memory device. ### Claim 7 (depends on 1) The method of claim 1, wherein the event-based information comprises a counter and the method further comprises: updating the counter based on accessing the memory row; incrementing the counter internally within the first memory device based on a refresh of the memory row; and resetting the counter based on a write to the memory row. ### Claim 8 (depends on 1) The method of claim 1, wherein the event-based information is provided to the memory controller in one or more previously unused interface transfer bits. ### Claim 9 (depends on 1) The method of claim 1, further comprising: storing one or more sensor values in the event-based information. ### Claim 10 A memory system comprising: a memory controller; a plurality of memory devices operably coupled to the memory controller; and a first memory device operably coupled to the memory controller, the first memory device configured to: generate, within the first memory device, a plurality of event-based information associated with activity in the memory system; store the event-based information in a reserved portion of the first memory device; and provide the event-based information to the memory controller corresponding with an access of a memory row across the plurality of memory devices associated with the event-based information. ### Claim 11 (depends on 10) The memory system of claim 10, wherein the first memory device stores an interface error correcting code (ECC) for the memory row in combination with the event-based information, wherein the interface ECC is computed across the memory devices by the memory controller. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the memory system is further configured to: store an internally-generated device ECC in the first memory device and in each of the plurality of memory devices; check the internally-generated device ECC in the first memory device and in each of the plurality of memory devices upon a read operation; and internally correct an error detected in a value read from the first memory device or the plurality of memory devices based on the internally-generated device ECC prior to sending the value to the memory controller. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the event-based information is updated based on an access to the internally-generated device ECC in the first memory device. ### Claim 14 (depends on 11) The memory system of claim 11, wherein the plurality of memory devices store data, and the event-based information is transferred across a plurality of beats of a multi-beat burst to the memory controller including data from the memory row and the interface ECC. ### Claim 15 (depends on 11) The memory system of claim 11, wherein the first memory device is further configured to dynamically remap an interface of the first memory device to switch between outputting the interface ECC and the event-based information on a bit line of the first memory device. ### Claim 16 (depends on 10) The memory system of claim 10, wherein the event-based information comprises a counter, the counter is updated based on accessing the memory row, the counter is incremented internally within the first memory device based on a refresh of the memory row, and the counter is reset based on a write to the memory row. ### Claim 17 (depends on 10) The memory system of claim 10, wherein the event-based information is provided to the memory controller in one or more previously unused interface transfer bits. ### Claim 18 (depends on 10) The memory system of claim 10, wherein one or more sensor values are stored in the event-based information. ### Claim 19 A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to perform: generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system; storing the event-based information in a reserved portion of the first memory device; and providing the event-based information to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein the program instructions executable by processing circuitry further cause the processing circuitry to perform: storing an interface error correcting code (ECC) for the memory row in the first memory device in combination with the event-based information, wherein the interface ECC is computed across the memory devices by the memory controller; storing an internally-generated device ECC in the first memory device and in each of the plurality of memory devices; checking the internally-generated device ECC in the first memory device and in each of the plurality of memory devices upon a read operation; and internally correcting an error detected in a value read from the first memory device or the plurality of memory devices based on the internally-generated device ECC prior to sending the value to the memory controller.