# US 2019/0171508 A1 · Logic buffer for hitless single event upset handling

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- Number: US 2019/0171508 A1
- Document ID: US20190171508A1
- Status: Published application
- Kind: A1
- Application number: 15/829,542
- Filed: 2017-12-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Arista Networks, Inc.
- Applicants: Arista Networks, Inc.
- Inventors: David Anthony Cananzi; Elliott B. Van Hartingsveldt; Michael Romain
- Web page: https://patentgrep.com/patent/US20190171508A1

## CPC

- G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)}
- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/0766: {Error or fault reporting or storing}
- G06F 11/183: {by voting, the voting not being performed by the redundant components}
- G11C 5/005: {Circuit means for protection against loss of information of semiconductor storage devices}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

## Claims

### Claim 1

A method for handling a single event upset (SEU), the method comprising:
receiving, from a monitored device, a first data at a first input of an initial state change device;
detecting, based on receiving the first data, a first state change;
asserting, based on detecting the first state change, an initial state change device enable signal;
transferring the first data from the first input to a first output of the initial state change device, wherein the first output is operatively connected to a second input of a state hold device;
triggering, based on detecting the first state change, a delay counter to count a delay period;
making, by a validation engine, a first determination that the delay period counted by the delay counter has expired without receipt of an error detection signal; and
based on the first determination, asserting a state hold device enable signal to allow the first data to pass from the second input to a second output of the state hold device.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the second output is operatively connected to a controlled device, and
the controlled device performs an action based on receiving the first data from the second output.

### Claim 3 (depends on 1)

The method of claim 1, further comprising, after asserting the state hold device enable signal to allow the first data to pass from the second input to the second output of the state hold device:
receiving, from the monitored device, a second data at the first input;
detecting, based on receiving second data, a second state change;
asserting, based on detecting the second state change, the initial state change device enable signal for the initial state change device to transfer the second data from the first input to the first output operatively connected to the second input;
triggering, based on detecting the second state change, the delay counter to count the delay period;
receiving, at the validation engine, while the delay counter is counting the delay period, the error detection signal;
making a second determination, based on receiving the error detection signal, not to assert the state hold device enable signal, causing the second data not to be transferred from the second input to the second output, and the first data to be held at the second output; and
sending an alert to a processor of a network device that that the error detection signal was received.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the second output is operatively connected to a controlled device, and
the controlled device remains in a prior state based on not receiving the second data from the second output.

### Claim 5 (depends on 3)

The method of claim 3, wherein the error detection signal is a cyclic redundancy check (CRC) asserted signal.

### Claim 6 (depends on 5)

The method of claim 5, wherein a duration of the delay period is based on a multiple of a time for completing a CRC for the monitored device.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the initial state change device comprises a shift register, and
detecting the first state change comprises detecting that a quantity of bits have been shifted into the shift register.

### Claim 8 (depends on 8)

The method of claim 8, wherein:
detecting that the quantity of bits have been shifted into the shift register is performed by the monitored device, and
the initial state change device enable signal is a load signal asserted by the monitored device to the delay counter.

### Claim 9 (depends on 1)

The method of claim 1, wherein:
the initial state change device comprises a latch, and
detecting the first state change comprises detecting, by a state comparator, a state change at a latch input of the latch.

### Claim 10

A system for handling a single event upset (SEU), the system comprising:
a monitored device comprising static random access memory (SRAM) comprising stored logic;
an initial state change device operatively connected to the monitored device, comprising a first input and a first output, and configured to receive a first data from the monitored device at the first input;
a state hold device comprising a second input and a second output, wherein the second input is operatively connected to the first output;
a delay counter configured to count a delay period;
the state comparator operatively connected to the first input, the initial state change device enable input of the initial state change device, and the delay counter, and configured to:
detect, based receiving the first data, a first state change;
assert, based on detecting the first state change, an initial state change device enable signal for the initial state change device to transfer the first data from the first input to the first output; and
trigger, based on detecting the first state change, the delay counter to count the delay period;
a validation engine operatively connected to the monitored device, the delay counter, and the state hold device, and configured to:
make a first determination that the delay period counted by the delay counter expired without receipt, by the validation engine, of an error detection signal from the monitored device; and
based on the first determination that no error detection signal was received during the delay period, assert a state hold device enable signal to allow the first data to pass from the second input to the second output of the state hold device.

### Claim 11 (depends on 10)

The system of claim 10, further comprising:
a controlled device operatively connected to the second output and configured to perform an action based on receiving the first data from the second output.

### Claim 12 (depends on 11)

The system of claim 11, wherein:
the initial state change device is further configured to:
receive a second data from the monitored device at the first input; and
transfer the second data from the first input to the first output based on receipt of the initial state change device enable signal from the state comparator,
the state comparator is further configured to:
detect a second state change based on receiving the second data;
assert, based on the detection of the second state change, the initial state change device enable signal;
trigger the delay counter to count the delay period, and
the validation engine is further configured to, after asserting the state hold device enable signal to allow the first data to pass from the second input to the second output of the state hold device:
receive, while the delay counter is counting the delay period, the error detection signal from the monitored device;
make a second determination, based on receipt of the error detection signal, not to assert the state hold device enable signal, causing the second data not to be transferred from the second input to the second output, and the first data to be held at the second output; and
send an alert to a processor of a network device that the error detection signal was received.

### Claim 13 (depends on 10)

The system of claim 10, wherein the monitored device is one selected from a group of monitored devices consisting of a field programmable gate array (FPGA) and a complex programmable logic device (CPLD).

### Claim 14 (depends on 13)

The system of claim 13, wherein the error detection signal comprises a cyclic redundancy check (CRC) assert signal sent by the FPGA to the validation engine.

### Claim 15 (depends on 10)

The system of claim 10, wherein the monitored device is a component of a switch.

### Claim 16 (depends on 10)

The system of claim 10, wherein the initial state change device comprises a first latch and the state hold device comprises a second latch.

### Claim 17 (depends on 10)

The system of claim 10, wherein the monitored device, the initial state change device, the state hold device, the delay counter, the state comparator, the validation engine, and the controlled device are each included as a part of a network device.

### Claim 18

A system for handling a single event upset (SEU), the system comprising:
a monitored device comprising static random access memory (SRAM) comprising stored logic;
an initial state change device operatively connected to the monitored device, comprising a first input and a first output, and configured to receive a first data from the monitored device at the first input;
a state hold device comprising a second input and a second output, wherein the second input is operatively connected to the first output;
a delay counter configured to:
receive a first load signal from the monitored device when a first state change occurs; and
count a delay period after receiving the first load signal;
a validation engine operatively connected to the monitored device, the delay counter, and the state hold device, and configured to:
make a first determination that the delay period counted by the delay counter expired without receipt, by the validation engine, of an error detection signal from the monitored device; and
based on the first determination, assert a state hold device enable signal to allow the first data to pass from the second input to the second output of the state hold device.

### Claim 19 (depends on 18)

The system of claim 18, wherein:
the initial state change device is further configured to:
receive a second data from the monitored device at the first input; and
transfer the second data from the first input to the first output,
the delay counter is further configured to:
receive a second load signal from the monitored device when a second state change occurs; and
count the delay period after receiving the second load signal, and
the validation engine is further configured to:
receive, while the delay counter is counting the delay period, the error detection signal;
make a second determination, based on receipt of the error detection signal, not to assert the state change device enable signal, causing the second data not to be transferred from the second input to the second output, and the first data to be held at the second output; and
send an alert to a processor of a network device that the error detection signal was received.

### Claim 20 (depends on 18)

The system of claim 18, wherein the initial state change device comprises a shift register and the state hold device comprises a storage register.

### Claim 21 (depends on 20)

The system of claim 20, wherein the monitored device, the initial state change device, the state hold device, the delay counter, the state comparator, the validation engine, and the controlled device are each included as a part of a network device.