# US 2019/0171506 A1 · Recovery of partial memory die

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- Number: US 2019/0171506 A1
- Document ID: US20190171506A1
- Status: Published application
- Kind: A1
- Application number: 15/834,050
- Filed: 2017-12-06
- Published: 2019-06-06
- Earliest claimed: 2017-12-06
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Sukhminder Singh Lobana; Kirubakaran Periyannan
- Web page: https://patentgrep.com/patent/US20190171506A1

## CPC

- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0754: {by exceeding limits}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 29/76: {using address translation or modifications}
- G11C 29/808: {using a flexible replacement scheme}
- G11C 29/88: {with partially good memories}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7206: Reconfiguration of flash memory system
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A partial memory die is removed from an edge of a wafer such that the partial memory die is missing a portion of the memory structure that was not printed on the wafer. A usable portion of the incomplete memory structure is determined and one or more rectangular zones in the usable portion of the incomplete memory structure are identified. During operation of the memory system, the memory system receives logical addresses for memory operations to be performed on the partial memory die and determines physical addresses that corresponding to the logical addresses. The memory system performs an out of bounds response for a physical address that is on the partial memory die but outside of the one or more rectangular zones. The memory system performs memory operations for physical addresses that are inside the one or more rectangular zones.

## Claims

### Claim 1

An apparatus, comprising:
an incomplete memory array on a partial memory die;
an operation adjustment circuit configured to modify a memory operation in response to the memory operation targeting memory cells outside a first usable zone of the incomplete memory array; and
a control circuit connected to the incomplete memory array, the control circuit configured to perform the memory operation in the first usable zone of the incomplete memory array.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
one or more storage devices configured to store boundary information of the first usable zone of the incomplete memory array.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein:
the operation adjustment circuit configured to adjust a width of data to be operated on in the memory operation based on the boundary information of the first usable zone.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein:
the boundary information of the first usable zone includes an indication of bit lines and an indication of erase blocks.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit configured to determine whether an address for the memory operation is within the first usable zone and perform an out of bounds response if the address is on the partial memory die but outside of any usable zone.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein:
the control circuit configured to determine whether the address for the memory operation is within the first usable zone of the incomplete memory structure by determining whether an erase block corresponding to the address is within a range of usable erase blocks and a bit line corresponding to the address is within a range of usable bit lines.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein:
the incomplete memory array includes multiple different sized usable zones, including the first usable zone; and
the control circuit is configured to determine which usable zone of the multiple different sized usable zones corresponds to the address.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein:
the control circuit is configured to adjust the width of a unit of data being operated on based on an indication of a range of bit lines for the first usable zone determined to correspond to the address.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is configured to not perform memory operations for addresses on the partial memory die but outside of any usable zone.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein:
the incomplete memory structure includes multiple planes of memory;
a first plane of the multiple planes of memory is complete; and
a second plane of the multiple planes of memory is incomplete, the second plane is missing components corresponding to components found in the first plane.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is one or more of a controller that is external to the partial memory die and a state machine on the partial memory die.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein:
the operation adjustment circuit is configured to remap a target address for the memory operation from an address outside the first usable zone to an address in the first usable zone.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein:
the operation adjustment circuit is configured adjust the unit of operation for the memory operation.

### Claim 14

A method comprising:
receiving logical addresses for memory operations to be performed on a partial memory die;
determining physical addresses corresponding to the logical addresses;
performing an out of bounds response for a physical address that is on the partial memory die but outside of a predetermined complete zone of the partial memory die; and
performing memory operations for physical addresses that are on the partial memory die and inside of the predetermined complete zone of the partial memory die.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
adjusting width of data to be programmed based on an indication of bit lines for an erase block in the predetermined complete zone of the partial memory die, the erase block is associated with a first address of the determined physical addresses and a program operation of the memory operations.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
choosing which complete zone of a plurality of different sized complete zones correspond to a given physical address; and
performing a memory operation in the chosen complete zone.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
removing the partial memory die from an edge of a wafer;
automatically identifying a usable portion of the partial memory die; and
dividing the usable portion of the partial memory die into the plurality of different sized complete zones.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
removing the partial memory die from an edge of a wafer;
automatically identifying a usable portion of the partial memory die; and
determining a rectangular zone in the usable portion of the partial memory die to be the predetermined complete zone.

### Claim 19

An apparatus, comprising:
an incomplete memory structure on a partial memory die;
means for storing boundary information of one or more usable zones of the incomplete memory structure; and
means for performing memory operations in the one or more usable zones based on the boundary information of one or more usable zones of the incomplete memory structure on the partial memory die.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein:
the incomplete memory structure comprises complete memory blocks and physically partial memory blocks; and
the physically partial memory blocks are missing substrate, memory cells and portions of bit lines corresponding to substrate, memory cells and portions of bit lines found in the complete memory blocks.