# US 2019/0171476 A1 · System and Method for Self-Protecting Data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171476 A1 - Document ID: US20190171476A1 - Status: Published application - Kind: A1 - Application number: 16/253,937 - Filed: 2019-01-22 - Published: 2019-06-06 - Earliest claimed: 2013-08-20 - Assignees: Teleputers, LLC - Applicants: Teleputers, LLC - Inventors: Ruby B. Lee; Pramod A. Jamkhedkar; Yu-Yuan Chen - Web page: https://patentgrep.com/patent/US20190171476A1 ## CPC - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 21/6227: {where protection concerns the structure of data, e.g. records, types, queries} - G06F 21/6281: {at program execution time, where the protection is within the operating system} - G06F 2009/45583: {Memory management, e.g. access or allocation} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed is a system comprising a physical memory, a processor and a software component. The software component includes a policy/domain handler for receiving data and a policy associated with the data; a hypervisor; and a file management module. The file management module receives a request from a third-party application to interact with a data file containing the data; sends an authorization and tag request to the policy/domain handler to check if the user and application are permitted to access the data, and if permitted, to generate hardware tags for the data file; and sends a secure data request to the hypervisor to create a secure data compartment for the data file and the hardware tags. Based on the authorization and tag request, and the security policy associated with the data, the policy/domain handler generates the hardware tags for the data file. Based on the secure data request, the hypervisor creates in the physical memory a secure data compartment containing the data file and the hardware tags, the hypervisor associating the hardware tags with the data in the secure data compartment. As the data is operated upon and moved to other memory areas, the hardware tags are propagated with the data according to tag propagation rules, and checked before performing operations that may lead to security breaches. ## Claims ### Claim 1 A method for reducing an amount of false positives in a dynamic implicit information flow tracking system performed by a computer system comprising a memory and a processor, the method comprising the steps of: determining whether a first branch instruction comprises a first tag indicative of conditional execution; setting a counter to a first maximum value if the first branch is tagged for conditional execution; propagating the first tag to branch instructions to be executed; decreasing a set counter first maximum value by one each time a branch instruction is executed; and clearing the set counter first maximum value and terminating propagation of the first tag to the branch instructions when the set counter first maximum value is zero. ### Claim 2 (depends on 1) The method of claim 1, further comprising: determining whether a second branch instruction comprises a second tag indicative of conditional execution; setting the counter to a second maximum value if the second branch instruction is tagged for conditional execution; propagating the second tag to branch instructions to be executed; decreasing a set counter second maximum value by one each time a branch instruction is executed; and clearing the set counter second maximum value and terminating the propagation of the second tag to the branch instructions when the set counter second maximum value is zero. ### Claim 3 (depends on 1) The method of claim 1, further comprising saving and restoring register file tags when the processor changes a privilege level. ### Claim 4 (depends on 1) The method of claim 1, further comprising terminating propagation of the first tag to the branch instructions to be executed by a software-inserted instruction. ### Claim 5 (depends on 1) The method of claim 1, wherein clearing the set counter first maximum value declassifies a sensitivity of data operated on by the first branch instruction. ### Claim 6 (depends on 1) The method of claim 1, further comprising executing a loop peeling process to match a number of pushes of a counter stack and a number of pops of the counter stack when the first branch instruction comprises at least one nested branch instruction tagged for conditional execution. ### Claim 7 A system for reducing an amount of false positives in a dynamic implicit information flow tracking system comprising: a memory; a counter; and a processor in communication with the memory and the counter and configured to: determine whether a first branch instruction comprises a first tag indicative of conditional execution; set the counter to a first maximum value when the first branch instruction is tagged for conditional execution; and control, based on the set counter first maximum value, propagation of the first tag to branch instructions to be executed. ### Claim 8 (depends on 7) The system of claim 7, wherein the processor is further configured to: decrease the set counter first maximum value by one each time a branch instruction is executed; and clear the set counter first maximum value and terminate the propagation of the first tag to the branch instructions to be executed when the set counter first maximum value is zero. ### Claim 9 (depends on 8) The system of claim 8, wherein the processor is further configured to: determine whether a second branch instruction comprises a second tag indicative of conditional execution; set the counter to a second maximum value when the second branch instruction is tagged for conditional execution; propagate the second tag to branch instructions to be executed; decrease the set counter second maximum value by one each time a branch instruction is executed, and clear the set counter second maximum value and terminate the propagation of the second tag to the branch instructions to be executed when the set counter second maximum value is zero. ### Claim 10 (depends on 7) The system of claim 7, wherein: the counter is a 32-bit count down counter; and the memory is a 32-bit register configured to store the first maximum value. ### Claim 11 (depends on 7) The system of claim 7, wherein the termination of the propagation of the first tag to the branch instructions to be executed is executed by a software-inserted instruction. ### Claim 12 (depends on 7) The system of claim 7, wherein clearance of the set counter first maximum value declassifies a sensitivity of data operated on by the first branch instruction. ### Claim 13 (depends on 7) The system of claim 7, further comprising a counter stack wherein the processor is further configured to execute a loop peeling process to match a number of pushes of the counter stack and a number of pops of the counter stack when the first branch instruction comprises at least one nested branch instruction tagged for conditional execution. ### Claim 14 A system for reducing an amount of false positives in a dynamic implicit information flow tracking system comprising: a processor in communication with a memory and configured to determine whether a first branch instruction comprises a first tag indicative of conditional execution; set a counter to a first maximum value when the first branch instruction is tagged for conditional execution; propagate the first tag to branch instructions to be executed; decrease the set counter first maximum value by one each time a branch instruction is executed; and clear the set counter first maximum value and terminate propagation of the first tag to the branch instructions to be executed when the set counter first maximum value is zero. ### Claim 15 (depends on 14) The system of claim 14, wherein the processor is further configured to determine whether a second branch instruction comprises a second tag indicative of conditional execution; set the counter to a second maximum value when the second branch instruction is tagged for conditional execution; propagate the second tag to branch instructions to be executed; decrease the set counter second maximum value by one each time a branch instruction is executed; and clear the set counter second maximum value and terminate the propagation of the second tag to the branch instructions to be executed when the set counter second maximum value is zero. ### Claim 16 (depends on 14) The system of claim 14, wherein clearance of the set counter first maximum value declassifies a sensitivity of data operated on by the first branch instruction. ### Claim 17 (depends on 14) The system of claim 14, wherein termination of the propagation of the first tag to the branch instructions to be executed is executed by a software-inserted instruction. ### Claim 18 (depends on 14) The system of claim 14, wherein the processor is further configured to execute a loop peeling process to match a number of pushes of a counter stack and a number of pops of the counter stack when the first branch instruction comprises at least one nested branch instruction tagged for conditional execution.