# US 2019/0171458 A1 · Performance scaling for binary translation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171458 A1 - Document ID: US20190171458A1 - Status: Published application - Kind: A1 - Application number: 16/273,080 - Filed: 2019-02-11 - Published: 2019-06-06 - Earliest claimed: 2017-06-02 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Hee jun Park; Mehmet Iyigun - Web page: https://patentgrep.com/patent/US20190171458A1 ## CPC - G06F 9/30174: {for non-native instruction set, e.g. Javabyte, legacy code} - G06F 8/52: Binary to binary - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30083: {Power or thermal control instructions} - G06F 9/3009: {Thread control instructions} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 A method performed by a computing device comprising storage hardware and processing hardware, the method performed by the processing hardware executing instructions stored in the storage hardware, the method comprising: executing an operating system kernel that manages assignment of execution units on the processing hardware, wherein the processing hardware comprises a processor that natively implements a target instruction set architecture (ISA), the processor comprising a plurality of cores, the plurality of cores comprising at least one big core and at least one little core, the big core having higher execution performance and power consumption than the little cores, wherein the execution units comprise (i) translated execution units comprised of instructions in the target ISA that have been translated from instructions in a source ISA, and (ii) non-translated execution units comprised of instructions in the target ISA that have not been translated to the target ISA; and wherein the managing the assignment of the execution units on the processing hardware by the kernel comprises assigning, based at least in part on the execution units being the translated execution units, the translated execution units to be executed by the big cores rather than the little cores. ### Claim 22 (depends on 21) A method according to claim 21, wherein the assigning comprises scheduling, by the kernel, the execution units to execute on the big core and the little core. ### Claim 23 (depends on 22) A method according to claim 22, wherein each of the big cores are configured to execute any given execution unit faster than each of the little cores. ### Claim 24 (depends on 21) A method according to claim 21, wherein the execution units comprise threads. ### Claim 25 (depends on 24) A method according to claim 24, wherein the kernel manages flags indicating which threads comprise translated execution units. ### Claim 26 (depends on 21) A method according to claim 21, wherein the causing the translated execution units to be executed by the big cores is further based on load associated with the translated execution units. ### Claim 27 A computing device comprising: processing hardware comprising a processor comprising a big core and a little core, the processor configured to implement a native instruction set architecture (ISA), wherein the big core has higher performance and power consumption than the little core; storage hardware storing an operating system comprising a loader and a kernel, and storing executable files, the executable files comprising compiled code comprising machine instructions, the loader configured to load the executable files, the kernel configured to allocate memory to store instructions loaded by the loader from the executable files; the memory hardware from which the memory is allocated, the memory hardware configured to store the instructions of the executable files loaded by the loader; and the kernel configured to control which of the big core and the little core executes the instructions in memory based on whether the instructions have been translated from machine instructions in a non-native ISA not implemented by the processor. ### Claim 28 (depends on 27) A computing device according to claim 27, wherein the kernel causes the big core to execute the translated machine instructions and the little core to execute the non-translated machine instructions. ### Claim 29 (depends on 28) A computing device according to claim 28, wherein the kernel causes the big core to execute the translated machine instructions by scheduling the translated machine instructions on the big core. ### Claim 30 (depends on 27) A computing device according to claim 27, wherein the processing hardware (i) executes the machine instructions translated from non-native ISA on the big core and (ii) executes non-translated machine instructions on the little core. ### Claim 31 (depends on 27) A computing device according to claim 27, wherein the kernel is configured to determine which instructions have been translated and accordingly schedule the translated instructions on the big core. ### Claim 32 (depends on 27) A computing device according to claim 27, wherein the control for translated machine instructions is further based on a measured load or a predicted load. ### Claim 33 (depends on 27) A computing device according to claim 27, wherein translated instructions comprise binary-translated code that was translated from an ISA not supported by the processor. ### Claim 34 (depends on 33) A computing device according to claim 33, wherein the translated instructions are identified by respective indications thereof, and wherein the kernel schedules execution of the machine instructions according to the corresponding indications. ### Claim 35 A method performed by a computing device, the method comprising: executing an operating system that schedules the execution of execution units by a processor that implements a native instruction set architecture (ISA), the processor comprising a big core and a little core, the big core configured for higher performance and power consumption than the little core; and executing the execution units by causing the translated execution units, when executing, to execute on the big core, and by causing the non-translated execution units, when executing, to execute on the little core, the instructions of the translated execution units translated from binary instructions compiled to execute for a non-native ISA, the processor not configured to implement the non-native ISA. ### Claim 36 (depends on 35) A method according to claim 35, wherein the non-translated execution units are caused to execute on the little core based on not being translated code, and wherein the translated execution units are caused to execute on the big core based on being translated code. ### Claim 37 (depends on 35) A method according to claim 35, wherein the execution units comprise threads, and wherein the operating system manages flags indicating which threads comprise translated execution units. ### Claim 38 (depends on 37) A method according to claim 37, wherein the causing comprises scheduling translated threads to execute on the big core rather than on the little core depends at least on the corresponding flag indicating the thread comprises translated execution units. ### Claim 39 (depends on 35) A method according to claim 35, wherein each of the execution units has a respective flag and the flags differ according to whether the execution units are translated or non-translated. ### Claim 40 (depends on 35) A method according to claim 35, wherein, for a given execution unit, whether the given execution unit is executed on the big core or the little core depends at least on whether the given execution unit is translated and on a performance characteristic of the given execution unit.