# US 2019/0171452 A1 · System and method for load fusion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171452 A1 - Document ID: US20190171452A1 - Status: Published application - Kind: A1 - Application number: 15/828,708 - Filed: 2017-12-01 - Published: 2019-06-06 - Earliest claimed: 2017-12-01 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: John M. King - Web page: https://patentgrep.com/patent/US20190171452A1 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/24: Loading of the microprogram - G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX} - G06F 9/3004: {to perform operations on memory} - G06F 9/3017: {Runtime instruction translation, e.g. macros} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/34: Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/384: {Register renaming} - G06F 9/3842: {Speculative instruction execution} - G06F 9/3867: {using instruction pipelines} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method for load fusion fuses small load operations into fewer, larger load operations. The system detects that a pair of adjacent operations are consecutive load operations, where the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive load micro-operations refers to both of the adjacent micro-operations being load micro-operations. The consecutive load operations are then reviewed to determine if the data sizes are the same and if the load operation addresses are consecutive. The two load operations are then fused together to form one load micro-operation with twice the data size and one load data micro-operation with no load component. ## Claims ### Claim 1 A method for fusing load micro-operations, the method comprising: determining whether adjacent micro-operations are consecutive load micro-operations, wherein the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive load micro-operations refers to both of the adjacent micro-operations being load micro-operations; determining whether the consecutive load micro-operations have a same data size; determining whether the consecutive load micro-operations are accessing consecutive addresses; and fusing the consecutive load micro-operations into a load micro-operation with twice the data size and a load data only micro-operation. ### Claim 2 (depends on 1) The method of claim 1, wherein the load data only micro-operation suppresses use of load queue entries and address generation scheduler queue entries. ### Claim 3 (depends on 1) The method of claim 1, further comprising: reviewing an addressing mode of each the consecutive micro-operations. ### Claim 4 (depends on 1) The method of claim 1, wherein the consecutive load micro-operation having a lower address is converted to the load micro-operation with twice the data size. ### Claim 5 (depends on 4) The method of claim 4, wherein the consecutive load micro-operation having a higher address is converted to the load data only micro-operation. ### Claim 6 (depends on 1) The method of claim 1, further comprising: marking fused loads as ineligible for memory renaming when memory renaming operates after load fusion. ### Claim 7 (depends on 1) The method of claim 1, further comprising: marking a memory renamed load micro-operation as ineligible when memory renaming operates before load fusion. ### Claim 8 (depends on 1) The method of claim 1, wherein an occurrence of an exception with respect to at least one of the load micro-operation with twice the data size and the load data only micro-operation results in re-execution of the adjacent micro-operations without fusing. ### Claim 9 (depends on 1) The method of claim 1, further comprising: providing an allocated destination physical register tag for the load data only micro-operation as additional payload for the load micro-operation with data size 2x. ### Claim 10 (depends on 9) The method of claim 9, further comprising: sending a LO portion of load results with a destination physical register tag in a first cycle; and sending a HI portion of the load results with a destination physical register tag of the load data only micro-operation in a second cycle. ### Claim 11 (depends on 1) The method of claim 1, further comprising: inserting a bubble into a load pipeline on a cycle immediately following a fused load micro-operation to allow the fused load micro-operation an extra cycle to process a HI portion of load results. ### Claim 12 A processor for fusing load micro-operations, comprising: a dispatch logic configured to dispatch micro-operations; and a load fusion detection logic connected to the dispatch logic, the load fusion detection logic configured to: determine whether adjacent micro-operations are consecutive load micro-operations, wherein the adjacent micro-operations refers to micro-operations flowing through adjacent dispatch slots and the consecutive load micro-operations refers to both of the adjacent micro-operations being load micro-operations; determine whether the consecutive load micro-operations have a same data size; determine whether the consecutive load micro-operations are accessing consecutive addresses; and fuse the consecutive load micro-operations into a load micro-operation with twice the data size and a load data only micro-operation. ### Claim 13 (depends on 12) The processor of claim 12, wherein the load data only micro-operation suppresses use of load queue entries and address generation scheduler queue entries. ### Claim 14 (depends on 12) The processor of claim 12, wherein the load fusion detection logic is configured to convert the consecutive load micro-operation having a lower address to the load micro-operation with twice the data size and the consecutive load micro-operation having a higher address to the load data only micro-operation. ### Claim 15 (depends on 12) The processor of claim 12, wherein the processor is further configured to mark fused loads as ineligible for memory renaming when memory renaming operates after load fusion. ### Claim 16 (depends on 12) The processor of claim 12, wherein the processor is further configured to mark a memory renamed load micro-operation as ineligible when memory renaming operates before load fusion. ### Claim 17 (depends on 12) The processor of claim 12, wherein an occurrence of an exception with respect to at least one of the load micro-operation with twice the data size and the load data only micro-operation results in re-execution of the adjacent micro-operations without fusing. ### Claim 18 (depends on 12) The processor of claim 12, wherein the load fusion detection logic is configured to provide an allocated destination physical register tag for the load data only micro-operation as additional payload for the load micro-operation with data size 2x. ### Claim 19 (depends on 12) The processor of claim 12, further comprising: a load fusion cycle logic, the load fusion cycle logic configured to: send a LO portion of load results with a destination physical register tag in a first cycle; and send a HI portion of the load results with a destination physical register tag of the load data only micro-operation in a second cycle. ### Claim 20 (depends on 12) The processor of claim 12, wherein the load fusion detection logic is configured to insert a bubble into a load pipeline on a cycle immediately following a fused load micro-operation to allow the fused load micro-operation an extra cycle to process a HI portion of load results.