# US 2019/0171389 A1 · Streamed program commands with periodic garbage collection

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- Number: US 2019/0171389 A1
- Document ID: US20190171389A1
- Status: Published application
- Kind: A1
- Application number: 15/829,870
- Filed: 2017-12-01
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: RAMANATHAN MUTHIAH; BALAJI THRAKSHA VENKATARAMANAN; RAMKUMAR RAMAMURTHY; RAVI GAJA
- Web page: https://patentgrep.com/patent/US20190171389A1

## CPC

- G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Apparatuses, systems, methods, and computer program products for streamed program commands with periodic garbage collection are disclosed. A controller is configured to set up a data path between the controller and a memory device to initialize an open mode. A controller is configured to perform a plurality of program operations on a memory device in an open mode using a same set up data path. A controller is configured to, in response to exiting an open mode, perform a garbage collection operation on a memory device.

## Claims

### Claim 1

An apparatus comprising:
a controller for a memory device, the controller configured to:
set up a data path between the controller and the memory device to initialize an open mode;
perform a plurality of program operations on the memory device in the open mode using the same set up data path; and
in response to exiting the open mode, perform a garbage collection operation on the memory device.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to perform the plurality of program operations without interruption for a garbage collection operation.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the controller is configured to exit the open mode in response to a trigger event, the trigger event comprising one or more of:
an amount of data stored by a single level cell (SLC) block satisfying a threshold;
an amount of data being accumulated for the garbage collection operation satisfying a threshold; and
a failure of one or more of the plurality of program operations.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the SLC block comprises one or more of a host write block and a fold destination block.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein, in response to the trigger event comprising the amount of data stored by the SLC block satisfying the threshold, the controller is configured to one of:
perform an erase operation on the SLC block and write new program data to the SLC block; and
perform an exchange operation to transfer valid program data stored in the SLC block to a different SLC block and write new program data to the SLC block.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein the failure comprises a program failure for a folding operation.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein, during the open mode, the controller is configured to:
receive program commands from a host computing device in communication with the controller; and
accumulate, in a command queue, a plurality of program commands received from the host computing device.

### Claim 8 (depends on 7)

The apparatus of claim 7, further comprising a set of memory latches for the memory device, wherein:
the program commands include program data; and
during the open mode, the controller is configured to, in response to the command queue accumulating at least a predetermined quantity of program commands, transmit the program data for the accumulated plurality of program commands to one or more memory latches of the set of memory latches.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein, during the open mode, the controller is configured to accumulate the transferred program data in the one or more memory latches until a memory latch of the one or more memory latches is one of full and includes at least a latch threshold amount of program data.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
the controller further comprises a flash translation layer (FTL) configured to track program data stored in the one or more memory latches; and
during the open mode, the controller is configured to:
write the program data to the memory device in response to the memory latch being the one of full and including greater than or equal to the latch threshold amount of program data, and
update the FTL in response to writing the program data to the memory device.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the program data is continuously transmitted to the one or more memory latches.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the controller is further configured to:
set up a new data path between the controller and the memory device to reinitialize the open mode; and
perform an additional plurality of program operations on the memory device in the reinitialized open mode using the new data path.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein:
the controller exits the open mode in response to a counter being incremented to a predetermined value; and
the counter is incremented in response to the controller performing each program operation of the plurality of program operations.

### Claim 14

A system comprising:
a memory device, comprising:
a memory array of memory elements; and
a set of memory latches for the memory array; and
a controller including a controller memory, the controller in communication with a host computing device and configured to:
receive memory commands including program data from the host computing device;
transmit the program data to one or more memory latches of the set of memory latches in a streaming write mode; and
in response to detecting one or more trigger events:
exit the streaming write mode; and
in response to exiting the streaming write mode, perform a garbage collection operation on the memory array.

### Claim 15 (depends on 14)

The system of claim 14, wherein the one or more trigger events comprise one or more of:
a single level cell (SLC) host write block being one of full and including at least a host write threshold amount of program data;
an SLC fold destination block being one of full and including at least a fold destination threshold amount of program data;
program data subject to the garbage collection operation being accumulated to satisfy a threshold amount; and
a program operation failure.

### Claim 16 (depends on 14)

The system of claim 14, wherein:
the one or more trigger events comprise at least a predetermined quantity of program data writes being performed on the memory array; and
the controller is further configured to:
in response to exiting the streaming write mode, pause transmitting the program data to the one or more memory latches in the streaming write mode, and
in response to completing the garbage collection operation:
set up a data path between the controller and the set of memory latches, and
resume transmitting the program data to the one or more memory latches in the streaming write mode.

### Claim 17 (depends on 16)

The system of claim 16, wherein:
the program data is continuously transmitted to the one or more memory latches; and
in response to a memory latch in the one or more memory latches being one of full and including at least a predetermined latch amount of the program data, the controller is further configured to write the program data in the memory latch to the memory array.

### Claim 18

An apparatus comprising:
means for transmitting program data to one or more memory latches of a set of memory latches for a memory array in an open mode;
means for exiting the open mode in response to detecting one or more trigger events; and
means for performing a garbage collection operation on the memory array in response to exiting the open mode.

### Claim 19 (depends on 18)

The apparatus of claim 18, further comprising means for detecting the one or more trigger events. wherein the one or more trigger events comprise one or more of:
a single level cell (SLC) host write block being one of full and including at least a host write threshold amount of program data;
an SLC fold destination block being one of full and including at least a fold destination threshold amount of program data;
program data subject to the garbage collection operation being accumulated to at least a garbage collection threshold amount; and
a program operation failure.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the one or more trigger events comprises at least a predetermined quantity of program data writes being performed on the memory array, the apparatus further comprising:
means for pausing transmission of the program data to the one or more memory latches in response to exiting the open mode;
means for setting up a data path between the means for transmitting and the set of memory latches in response to completing the garbage collection operation; and
means for resuming transmission of the program data to the one or more memory latches in response to setting up the data path.