# US 2019/0171385 A1 · Multi-partitioning of memories

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- Number: US 2019/0171385 A1
- Document ID: US20190171385A1
- Status: Published application
- Kind: A1
- Application number: 16/201,729
- Filed: 2018-11-27
- Published: 2019-06-06
- Earliest claimed: 2009-11-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Danilo Caraccio; Emanuele Confalonieri; Federico Tiziani
- Web page: https://patentgrep.com/patent/US20190171385A1

## CPC

- G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools}
- G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/0631: {by allocating resources to storage systems}
- G06F 3/0637: {Permissions}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)}
- G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G11C 14/009: {and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material}
- G06F 2212/2022: Flash memory
- G06F 2212/2024: Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
- G06F 2213/3804: Memory card connected to a computer port directly or by means of a reader/writer
- G06F 2213/3854: Control is performed at the peripheral side
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

## Claims

### Claim 1

A memory device, comprising:
first and second memory devices of different memory technologies; and
a first interface controller configured to be interposed between a memory bus and the first memory device, and a second interface controller configured to be interposed between the memory bus and the second memory device, the first interface controller configured to manage logical memory partitioning on at least the first memory device, the first and second controllers further configured to allocate data of a first attribute to the first memory device, and to allocate data of a second attribute to the second memory device.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first interface controller is configured to be aware of the existence of the second interface controller, and the second interface controller is configured not to be aware of the first interface controller.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first interface controller and the second interface controller each include a register management block to track memory partitions.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the first interface controller is configured to service all requests to access a user data area, an enhanced user data area, and all general-purpose partitions whose attribute parameter is not set.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the first interface controller and the second interface controller each connect directly to the memory bus.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first interface controller connects directly to the memory bus, and wherein the second interface controller is connected to the first interface controller.

### Claim 7 (depends on 4)

The memory device of claim 4, wherein the first interface controller includes a partition and mode configuration block to inhibit a response from the second interface controller, and to allow the first interface controller to generate a response across the memory bus to a memory controller unit host, the response to include error conditions related to the enhanced user data area.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the memory device comprises an embedded multi-media card (e-MMC) device.

### Claim 9

An embedded multi-media card (e-MMC) memory, comprising:
a non-volatile flash memory coupled to a first interface controller, the first interface controller to be coupled to an external memory controller unit; and
a Phase-Change Memory (PCM) coupled to a second interface controller, the second interface controller coupled to the first memory controller to manage commands referencing partitions set up in the e-MMC memory using a connection between the first interface controller and the second interface controller.

### Claim 10 (depends on 9)

The e-MMC memory of claim 9, wherein the non -volatile flash memory comprises NAND Flash memory.

### Claim 11 (depends on 10)

The e-MMC memory of claim 10, wherein the non-volatile flash memory comprises a number of Multi-Level Cell (MLC) devices.

### Claim 12 (depends on 9)

The e-MMC memory of claim 9, wherein:
the first interface controller is configured to be aware of the existence of the second interface controller; and
the second interface controller is configured not to be aware of the first controller.

### Claim 13 (depends on 9)

The e-MMC memory of claim 9, wherein:
the first interface controller is configured to manage commands to mapped portions of the non-volatile flash memory without an attribute enhanced set; and
the second interface controller is configured to reconfigure partitions of the PCM as directed by the external memory controller unit.

### Claim 14 (depends on 13)

The e-MMC memory of claim 13, wherein the second interface controller is configured to map the portions of the PCM with the attribute enhanced set.

### Claim 15 (depends on 9)

The e-MMC memory of claim 9, wherein a combination of memory types including the non-volatile flash memory and the PCM allows the e-MMC memory to access the non-volatile flash memory for mass storage applications d access the PCM for address-intensive applications.

### Claim 16 (depends on 15)

The e-MMC memory of claim 15, wherein the address-intensive applications include demand paging for code storage and execution.

### Claim 17

An embedded multi-media card (e-MMC) managed memory device, comprising:
a first interface controller and a second interface controller, the first interface controller configured to be coupled to an external memory controller unit host and to be aware of the existence of the second interface controller and the second interface controller configured not to be aware of the first interface controller, the first interface controller further configured to provide all responses to incoming commands received from the external memory controller unit host;
a first type of non-volatile memory coupled to the first interface controller; and
a second type of non-volatile memory coupled to the second interface controller to reconfigure partitions of the second type of non-volatile memory according to commands received from the external memory controller unit host.

### Claim 18 (depends on 17)

The e-MMC managed memory device of claim 17, wherein:
the first type of non-volatile memory comprises Multi-Level Cell (MLC) NAND flash memory; and
the second type of non-volatile memory comprises Phase-Change Memory (PCM).

### Claim 19 (depends on 17)

The eMMC managed memory device of claim 17, wherein, during a power management mode:
both the first interface controller and the second interface controller are configured to execute state transitions to an inactive state; and
only the first interface controller is to reply to the external memory controller unit host.

### Claim 20 (depends on 17)

The eMMC managed memory device of claim 17; wherein:
the second interface controller comprises a register to inhibit a response in the second interface controller; and
the first interface controller is configured to manage generating the response to the external memory controller unit host.

### Claim 21 (depends on 17)

The eMMC managed memory device of claim 17, wherein at least the first interface controller is to abstract the first type of non-volatile memory and the second type of non-volatile memory from the memory controller unit host, wherein the first interface controller connects directly to the memory bus, and wherein the second interface controller is connected to the first interface controller.