# US 2019/0171376 A1 · Permission control for contingent memory access program instruction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171376 A1 - Document ID: US20190171376A1 - Status: Published application - Kind: A1 - Application number: 16/309,190 - Filed: 2017-05-18 - Published: 2019-06-06 - Earliest claimed: 2016-06-29 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Nigel John STEPHENS; Grigorios MAGKLIS - Web page: https://patentgrep.com/patent/US20190171376A1 ## CPC - G06F 3/0622: {in relation to access} - G06F 3/0637: {Permissions} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 12/10: Address translation - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1483: {using an access-table, e.g. matrix or list} - G06F 16/21: Design, administration or maintenance of databases - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F 2212/1044: Space efficiency improvement - G06F 2212/657: Virtual address space management - G06F 2212/684: TLB miss handling - G06F 2221/2141: Access rights, e.g. capability lists, access control lists, access tables, access matrices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing apparatus and method serve to manage access permission checking in respect of contingent memory access operations (the access permission failure of which does not alter program flow) in dependence of a contingent-access permission checking disable flag. If the contingent access disable flag has a first value, then this disables memory permission circuitry e.g. a walk state machine 22, from performing a check as to whether or not the memory access circuitry is permitted to perform a requested memory access. Non-contingent memory accesses are able to utilise the memory permission circuitry irrespective of the value of the contingent-access permission checking disable flag. ## Claims ### Claim 1 Apparatus for processing data comprising: memory access circuitry responsive to a memory access program instruction of a program to perform one or more memory accesses within a memory address space, wherein when said memory access program instruction is a contingent memory access program instruction, said one or more memory accesses include at least one contingent memory access and program flow to a next program instruction to be executed following said contingent memory access program instructions is independent of whether said at least one contingent memory access is permitted; and when said memory access program instruction is a non-contingent memory access program instruction, said one or more memory accesses are one or more non-contingent memory accesses and program flow to a next program instruction to be executed following said non-contingent memory access program instructions is dependent upon whether said one or more non-contingent memory accesses is permitted; and memory permission circuitry to control whether said memory access circuitry is permitted to perform said memory access, wherein in respect of said one or more contingent memory accesses, said memory permission circuitry is responsive to a contingent-access permission checking disable flag having a first value to disable said control by said memory permission circuitry and to said contingent-access permission checking disable flag having a second value to enable said control by said memory permission circuitry; and in respect of said one or more non-contingent memory accesses, said control by said memory permission circuitry is independent of said contingent-access permission checking disable flag. ### Claim 2 (depends on 1) Apparatus as claimed in claim 1, wherein said memory permission circuitry is responsive to access permission data to control access to memory addresses within said memory address space. ### Claim 3 (depends on 1) Apparatus as claimed in claim 1, wherein said memory permission circuitry is part of a memory management unit and serves to perform permission table walking through permission table data. ### Claim 4 (depends on 2) Apparatus as claimed in claim 2, wherein said permission table data is translation table data that specifies virtual address to physical address mappings. ### Claim 5 (depends on 1) Apparatus as claimed in claim 1, wherein said contingent memory access program instruction is a contingent vector memory access instructions specifying a sequence of memory access operations and at least some of said sequence of memory access operations are contingent memory access operations. ### Claim 6 (depends on 5) Apparatus as claimed in claim 5, wherein a first memory access operation within said sequence of memory access operations is a non-contingent memory access operation and one or more other memory access operations within said sequence of memory access operations are contingent memory access operations. ### Claim 7 (depends on 6) Apparatus as claimed in claim 6, wherein said sequence of memory access operations are to non-contiguous addresses within said memory address space. ### Claim 8 (depends on 5) Apparatus as claimed in claim 5, wherein all of said sequence of memory access operations are contingent memory access operations. ### Claim 9 (depends on 8) Apparatus as claimed in claim 8, wherein said sequence of memory access operations are to contiguous addresses within said memory address space. ### Claim 10 (depends on 1) Apparatus as claimed in claim 1, wherein said memory address space comprises a first memory address region and a second memory address region, said memory permission circuitry is responsive to a first contingent-access permission checking disable flag to selectively disable operation of said memory permission circuitry in respective of contingent memory accesses within said first memory address region, and said memory permission circuitry is responsive to a second contingent-access permission checking disable flag to selectively disable operation of said memory permission circuitry in respective of contingent memory accesses within said second memory address region. ### Claim 11 (depends on 1) Apparatus as claimed in claim 1, comprising exception level control circuitry to control said apparatus to operate within a selectable one of a plurality of exception levels corresponding to respective privilege levels of operation. ### Claim 12 (depends on 2) Apparatus as claimed in claim 2, wherein two of said plurality of exception levels share access permission data. ### Claim 13 (depends on 1) Apparatus as claimed in claim 1, comprising an access permission cache to store access permission data and wherein, when said access permission cache stores access permission data matching said one or more contingent memory accesses, said access permission cache controls whether said memory access circuitry is permitted to perform said one or more contingent memory accesses independently of said contingent-access permission checking disable flag. ### Claim 14 A method of processing data comprising: in response to a memory access program instruction of a program, performing one or more memory accesses within a memory address space, wherein when said memory access program instruction is a contingent memory access program instruction, said one or more memory accesses include at least one contingent memory access and program flow to a next program instruction to be executed following said contingent memory access program instructions is independent of whether said at least one contingent memory access is permitted; and when said memory access program instruction is a non-contingent memory access program instruction, said one or more memory accesses are one or more non-contingent memory accesses and program flow to a next program instruction to be executed following said non-contingent memory access program instructions is dependent upon whether said one or more non-contingent memory accesses is permitted; controlling whether said memory access is permitted using memory permission circuitry, wherein in respect of said one or more contingent memory accesses, in response to a contingent-access permission checking disable flag having a first value, disabling said control by said memory permission circuitry and, in response to said contingent-access permission checking disable flag having a second value, enabling said control by said memory permission circuitry; and in respect of said one or more non-contingent memory accesses, said control by said memory permission circuitry is independent of said contingent-access permission checking disable flag. ### Claim 15 (depends on 1) A computer program for controlling a computer to provide a virtual machine execution environment corresponding to the apparatus according to claim 1.