# US 2019/0171048 A1 · Pixel structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0171048 A1 - Document ID: US20190171048A1 - Status: Published application - Kind: A1 - Application number: 16/152,352 - Filed: 2018-10-04 - Published: 2019-06-06 - Earliest claimed: 2017-12-05 - Assignees: Hannstar Display Corp. - Applicants: Hannstar Display Corporation - Inventors: Mu-Kai Kang - Web page: https://patentgrep.com/patent/US20190171048A1 ## CPC - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133512: {Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence)} - G02F 1/133514: {Colour filters} - G02F 1/13394: {spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence)} - G02F 1/134318: {having a patterned common electrode} - G02F 1/134381: {Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates} - G02F 2201/121: common or background - G02F 2201/123: pixel - G02F 2202/10: semiconductor - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A pixel structure includes a substrate, a thin film transistor and a common electrode. The thin film transistor is disposed on the substrate, wherein a semiconductive active layer of the thin film transistor has a channel region disposed between a source and a drain, the channel region includes a main channel region and at least one sub channel region, a channel length of the main channel region is less than a channel length of the at least one sub channel region, and the channel length of the main channel region is equal to a minimum of a channel length of the channel region. The common electrode is disposed on the thin film transistor, and the common electrode overlaps at least a portion of the at least one sub channel region, wherein the common electrode has an opening exposing the main channel region. ## Claims ### Claim 1 A pixel structure, comprising: a substrate having a surface; a thin film transistor disposed on the surface of the substrate, the thin film transistor comprising a gate, a source, a drain, a gate insulating layer and a semiconductive active layer, wherein the gate, the source and the drain respectively overlap a portion of the semiconductive active layer in a direction perpendicular to the surface, the gate insulating layer is disposed between the gate and the semiconductive active layer, the semiconductive active layer has a channel region disposed between the source and the drain, the channel region comprises a main channel region and at least one sub channel region, a channel length of the main channel region is less than a channel length of the at least one sub channel region, and the channel length of the main channel region is equal to a minimum of a channel length of the channel region, wherein the channel length of the channel region is a distance of the channel region from the drain to the source; and a common electrode disposed on the thin film transistor, the common electrode overlapping at least a portion of the at least one sub channel region, wherein the common electrode has an opening exposing the main channel region. ### Claim 2 (depends on 1) The pixel structure of claim 1, wherein a vertical projection of the common electrode on the surface does not overlap a vertical projection of the main channel region on the surface. ### Claim 3 (depends on 1) The pixel structure of claim 1, wherein a vertical projection of the opening on the surface is situated within a vertical projection of the semiconductive active layer on the surface. ### Claim 4 (depends on 1) The pixel structure of claim 1, wherein the opening exposes a portion of the at least one sub channel region. ### Claim 5 (depends on 1) The pixel structure of claim 1, wherein a distance between an edge of a vertical projection of the main channel region on the surface and an edge of a vertical projection of the opening on the surface is less than or equal to 2 μm. ### Claim 6 (depends on 1) The pixel structure of claim 1, further comprising: a pixel electrode disposed on the gate insulating layer and electrically connected to the drain of the thin film transistor; and a first insulating layer disposed between the pixel electrode and the common electrode. ### Claim 7 (depends on 6) The pixel structure of claim 6, wherein the common electrode is disposed on the first insulating layer and the pixel electrode. ### Claim 8 (depends on 6) The pixel structure of claim 6, further comprising a second insulating layer disposed between the pixel electrode and the gate insulating layer and disposed between the common electrode and the gate insulating layer. ### Claim 9 (depends on 8) The pixel structure of claim 8, wherein the pixel electrode is disposed between the first insulating layer and the second insulating layer, and the common electrode is disposed on the first insulating layer and the pixel electrode. ### Claim 10 (depends on 8) The pixel structure of claim 8, wherein the common electrode is disposed between the first insulating layer and the second insulating layer, and the pixel electrode is disposed on the first insulating layer and the common electrode. ### Claim 11 (depends on 8) The pixel structure of claim 8, wherein each of the first insulating layer and the second insulating layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride. ### Claim 12 (depends on 11) The pixel structure of claim 11, wherein the second insulating layer further comprises an organic insulating material. ### Claim 13 (depends on 6) The pixel structure of claim 6, wherein the semiconductive active layer comprises indium gallium zinc oxide (IGZO), and an oxygen content of a portion of the first insulating layer located closer to the semiconductive active layer is greater than an oxygen content of a portion of the first insulating layer located farther from the semiconductive active layer. ### Claim 14 (depends on 6) The pixel structure of claim 6, wherein the common electrode or the pixel electrode has a plurality of slits. ### Claim 15 (depends on 1) The pixel structure of claim 1, further comprising: a scan line extending along a first direction and electrically connected to the gate of the thin film transistor; and a data line extending along a second direction and electrically connected to the source of the thin film transistor, wherein the first direction is not parallel to the second direction, wherein the source has a first part and a second part, the first part comprises a portion of the data line, the second part protrudes from the data line, and the source has a hook-shape. ### Claim 16 (depends on 1) The pixel structure of claim 1, wherein the source has a bending shape or a curved shape. ### Claim 17 (depends on 1) The pixel structure of claim 1, wherein the common electrode is provided with a common voltage, and the common voltage is less than or equal to 0 volts. ### Claim 18 (depends on 1) The pixel structure of claim 1, wherein the channel length of the main channel region ranges from 2.5 μm to 5.5 μm. ### Claim 19 (depends on 1) The pixel structure of claim 1, wherein the semiconductive active layer comprises one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium zinc oxide (IZO), gallium oxide, cadmium oxide, magnesium oxide, calcium oxide, strontium oxide, barium oxide, titanium oxide, tantalum oxide, aluminum oxide, indium oxide, niobium oxide, hafnium oxide, tin oxide, zinc oxide, zirconium oxide, copper oxide, yttrium oxide, barium yttrium oxide, and samarium tin oxide or any combination thereof. ### Claim 20 (depends on 19) The pixel structure of claim 19, wherein the semiconductive active layer is indium gallium zinc oxide layer, and a portion of the gate insulating layer located closer to the semiconductive active layer comprises silicate material. ### Claim 21 A the pixel structure, comprising: a first substrate having a surface; a thin film transistor disposed on the surface of the first substrate, the thin film transistor comprising a gate, a source, a drain, a gate insulating layer and a semiconductive active layer, wherein the gate, the source and the drain overlap a portion of the semiconductive active layer in a direction perpendicular to the surface respectively, the gate insulating layer is disposed between the gate and the semiconductive active layer, the semiconductive active layer has a channel region disposed between the source and the drain, the channel region comprises a main channel region and at least one sub channel region, a channel length of the main channel region is less than a channel length of the at least one sub channel region, and the channel length of the main channel region is equal to a minimum of a channel length of the channel region, wherein the channel length of the channel region is referred to a distance of the channel region from the drain to the source; a first transparent conductive layer disposed on the thin film transistor, the first transparent conductive layer covering at least a portion of the at least one sub channel region, wherein the first transparent conductive layer has an opening exposing the main channel region; a second substrate disposed on the surface of the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. ### Claim 22 (depends on 21) The pixel structure of claim 21, further comprising a second transparent conductive layer disposed between the second substrate and the liquid crystal layer, wherein the second transparent conductive layer is provided with a common voltage.