# US 2019/0170818 A1 · Synchronized pulsed lada for the simultaneous acquisition of timing diagrams and laser-induced upsets

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0170818 A1
- Document ID: US20190170818A1
- Status: Published application
- Kind: A1
- Application number: 16/259,903
- Filed: 2019-01-28
- Published: 2019-06-06
- Earliest claimed: 2013-03-24
- Assignees: DCG Systems, Inc.; NXP USA, Inc.
- Applicants: DCG Systems, Inc.; NXP USA, Inc.
- Inventors: Kent Erington; Daniel J. Bodoh; Keith Serrels; Theodore Lundquist
- Web page: https://patentgrep.com/patent/US20190170818A1

## CPC

- G01R 31/311: of integrated circuits {(G01R31/31728 takes precedence)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

## Claims

### Claim 1

A laser assisted device alteration (LADA) system operable in conjunction with a testing equipment (TE) for testing integrated circuit device under test (DUT), comprising:
a controller configured to operate the timing electronics for timing the laser pulses to arrive at transistors in the DUT at times synchronized to the clock time and enable incorporating a delay or advance of the laser pulses with respect to the clock time, to thereby alter the transistors electrical response to test signals applied to the DUT from the TE, the controller being further configured to detect the altered transistors electrical response, receive the corresponding intensity signals, and utilize the electrical response and intensity signals to produce a plot of electrical response versus time for a selected location on the DUT; and
a single-pixel sensor detecting reflections of the laser pulses from the DUT and generating corresponding intensity signals.

### Claim 2 (depends on 1)

The system of claim 1, wherein the plot of electrical response versus time corresponds to the synchronization of laser pulses to the clock signal.

### Claim 3 (depends on 1)

The system of claim 1, wherein the plot of electrical response versus time comprises a plot of failure rate versus arrival time of the laser pulses relating to test signals of the TE.

### Claim 4 (depends on 1)

The system of claim 1, wherein the pulse rate of the laser pulses is configured as a multiple of the clock signal.

### Claim 5 (depends on 1)

The system of claim 1, wherein the optical arrangement directs the laser pulses onto desired locations by successively directing a train of laser pulses to each desired location to thereby illuminate a selected area of the DUT.

### Claim 6 (depends on 1)

The system of claim 1, wherein the pulsed laser source generates a beam of laser pulses and wherein the optical arrangement directs the laser pulses onto desired locations by successively parking the laser beam at each desired location.

### Claim 7 (depends on 1)

The system of claim 1, wherein the controller utilizes the electrical response and intensity signals by detecting a test failure or pass at each desired location, and when detecting a failure setting the intensity signal to a first color and when detecting a pass setting the intensity signal to a second color.

### Claim 8 (depends on 7)

The system of claim 7, wherein the first color is one of black and white and the second color is the other of black and white.

### Claim 9 (depends on 1)

The system of claim 1, wherein the controller further applied a Fourier Transform to the plot of electrical response versus time.

### Claim 10 (depends on 1)

The system of claim 1, further comprising a monitor, and wherein the controller displays on the monitor an image of an area of interest, wherein locations having transistors failing at above 50% rate are displayed as one color and locations having transistors failing at below 50% rate are displayed as second color; the controller further displaying on the monitor the plot of electrical response versus time for each selected one of the locations having transistors failing at above 50% rate and locations having transistors failing at below 50% rate.

### Claim 11

A method using laser assisted device alteration (LADA) for testing an integrated device under test (DUT) that is coupled to a testing equipment (TE) the TE generating a clock signal and a test signal, the method comprising:
generating a laser beam comprising a train of laser pulses;
sequentially positioning the laser beam on each pixel location within an area of interest of the DUT and performing a test loop at each pixel location, wherein the test loop comprises temporally scanning arrival time of the laser pulses with respect to the clock signal while the ATE applies the test signal to the DUT and for each spatiotemporal volume recording a pass/fail result of the DUT, wherein spatiotemporal volume is defined as a combination of a spatial coordinate on the DUT and arrival time of a laser pulse; and,
generating a plot of failure rate versus time for a plurality of pixel locations for which pass/fail results indicate a failure rate deviating from a predetermined value.

### Claim 12 (depends on 11)

The method of claim 11, wherein the laser pulses are configured to have wavelength and duration calculated to cause two-photon absorption within the DUT.

### Claim 13 (depends on 11)

The method of claim 11, wherein the laser pulses are configured to have wavelength and duration calculated to cause single-photon absorption within the DUT.

### Claim 14 (depends on 11)

The method of claim 11, wherein recording a pass/fail result of the DUT further comprises recording a first color when the DUT pass and recording a second color when the DUT fails.

### Claim 15 (depends on 14)

The method of claim 14, further comprising generating an image on a monitor using the first and second colors.

### Claim 16 (depends on 14)

The method of claim 14, wherein generating the plot of failure rate versus time comprises selecting a spatial coordinate on the DUT and plotting the first and second color versus time.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first color is one of black and white and the second color is the other of black and white.

### Claim 18 (depends on 11)

The method of claim 11, wherein the pixel location includes a flip-flop, and wherein the train of laser pulses is configured to generate a single-upset event in the flip-flop.

### Claim 19 (depends on 11)

The method of claim 11, further comprising correlating plurality of pixel locations for which pass/fail results indicate a failure rate deviating from 50% with layout of transistors in a netlist.

### Claim 20

A method using laser assisted device alteration (LADA) for testing an integrated device under test (DUT) that is coupled to a testing equipment (TE) the TE generating a clock signal and a test signal, the method comprising:
configuring the TE to apply to the DUT test pattern causing transistors in the DUT to fail at least one of the tests without the application of laser pulses;
applying the test pattern repetitively to the DUT while applying laser pulses at selected focus locations of the DUT, the laser pulses being configured to have sufficient energy to inject charge carrier pair at precise times during the test pattern;
recording the tester results for each test pattern repetition at each focus location;
determining locations where test results substantially diverge from 50% failure;
generating a sequence of failure rate versus time progression at locations wherein the failure rate substantially diverges.