# US 2019/0170814 A1 · Burn-in test device and test method using interposer

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- Number: US 2019/0170814 A1
- Document ID: US20190170814A1
- Status: Published application
- Kind: A1
- Application number: 16/013,382
- Filed: 2018-06-20
- Published: 2019-06-06
- Earliest claimed: 2017-12-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Joosung YUN
- Web page: https://patentgrep.com/patent/US20190170814A1

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/2862: {Chambers or ovens; Tanks}
- G01R 31/2863: {Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04)}
- G01R 31/2874: {related to temperature}
- G01R 31/2882: {Testing timing characteristics}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 29/06: Acceleration testing
- G11C 29/56004: {Pattern generation}
- G11C 29/56012: {Timing aspects, clock generation, synchronisation}
- G11C 29/56016: {Apparatus features}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A test device includes a connecting circuit and a chamber. The connecting circuit includes an interposer to transfer a test signal to operate a device under test. The chamber includes a pin electronic circuit to generate a control signal to control an operation of the device under test based on the test signal received through the interposer. The pin electronic circuit is spatially disposed within the chamber and generates the control signal. When the test signal is received, an internal temperature of the chamber is higher or lower than an external temperature of the chamber when the test signal is received.

## Claims

### Claim 1

A test device, comprising:
a connecting circuit including an interposer to transfer a test signal to operate a device under test; and
a chamber including a pin electronic circuit to generate a control signal to control an operation of the device under test based on the test signal received through the interposer, wherein the pin electronic circuit is spatially disposed within the chamber and generates the control signal, and wherein an internal temperature of the chamber is higher or lower than an external temperature of the chamber when the test signal is received.

### Claim 2 (depends on 1)

The test device as claimed in claim 1, wherein the pin electronic circuit is implemented with at least one of an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

### Claim 3 (depends on 1)

The test device as claimed in claim 1, further comprising:
a system circuit to generate the test signal based on a data signal and a timing signal from a host.

### Claim 4 (depends on 3)

The test device as claimed in claim 3, wherein the interposer is stacked between the system circuit and the chamber.

### Claim 5 (depends on 3)

The test device as claimed in claim 3, wherein:
the data signal corresponds to control of the operation of the device under test, and
the timing signal corresponds to a time interval where a logical value of the test signal is maintained.

### Claim 6 (depends on 3)

The test device as claimed in claim 3, wherein the system circuit includes:
an algorithm pattern generator to generate logic data to test the operation of the device under test based on the data signal.

### Claim 7 (depends on 6)

The test device as claimed in claim 6, wherein the system circuit further includes a timing generator to:
adjust a time interval, in which the test signal is maintained with a logical value of the logic data, based on the timing signal, and
output the test signal.

### Claim 8 (depends on 1)

The test device as claimed in claim 1, wherein:
the device under test includes a memory device to store data, and
the test signal corresponds to control of the memory device, an address of the memory device, and data to be stored at a location corresponding to the address.

### Claim 9

A test device, comprising:
a system circuit to generate a test signal to test an operation of a device under test based on a request of a host;
a chamber including a pin electronic circuit to generate a control signal to control the operation of the device under test based on the test signal; and
a connector to electrically connect the system circuit and the chamber by an interposer stacked between the system circuit and the chamber, wherein an internal temperature of the chamber is higher or lower than an external temperature of the chamber based on the request of the host to test the operation of the device under test.

### Claim 10 (depends on 9)

The test device as claimed in claim 9, wherein:
the device under test includes a memory device, and
the test signal is to control read and write operations of the memory device.

### Claim 11 (depends on 9)

The test device as claimed in claim 9, wherein the chamber includes:
a burn-in board to mount the device under test.

### Claim 12 (depends on 9)

The test device as claimed in claim 9, wherein the interposer includes a coupling part including a conductive material to transfer the test signal from the system circuit to the chamber.

### Claim 13 (depends on 9)

The test device as claimed in claim 9, wherein the system circuit includes a site board to:
receive a data signal and a timing signal from the host, and
generate the test signal based on the data signal and timing signal.

### Claim 14 (depends on 13)

The test device as claimed in claim 13, wherein the site board includes an algorithm pattern generator to:
receive the data signal from the host, and
generate logic data to control the operation of the device under test based on the data signal.

### Claim 15 (depends on 14)

The test device as claimed in claim 14, wherein the site board includes a timing generator to receive:
the timing signal from the host, and
adjust a time interval, in which a logical value of the timing signal is maintained, based on the timing signal and the logic data.

### Claim at position 16

-20. (canceled)

### Claim 21

A non-transitory, computer-readable medium comprising instructions which, when executed, cause a processor to perform a method of:
generating, by a system circuit of a test device, a test signal to test a device under test;
transferring the test signal through an interposer stacked between the system circuit and the test device;
generating, by a pin electronic circuit spatially disposed within a chamber, a control signal to control an operation of the device under test based on the test signal transferred through the interposer; and
testing the device under test based on the control signal at a temperature that is higher or lower than an external temperature of the chamber.

### Claim 22 (depends on 21)

The medium as claimed in claim 21, wherein transferring the test signal includes electrically connecting the system circuit and the chamber by the interposer.

### Claim 23 (depends on 21)

The medium as claimed in claim 21, further comprising:
receiving a request of a host by the system circuit; and
generating, by the system circuit, the test signal based on the request of the host.

### Claim 24 (depends on 21)

The medium as claimed in claim 21, wherein generating the test signal for testing the device under test includes:
receiving a data signal from a host at the system circuit;
generating, by the system circuit, logic data of a logical value to control the operation of the device under test based on the data signal;
receiving a timing signal from the host at the system circuit;
generating, by the system circuit, the test signal having the logical value of the logic data during a specific time interval based on the timing signal and the logic data; and
adjusting the specific time interval by the system circuit.

### Claim 25 (depends on 24)

The medium as claimed in claim 24, wherein the pin electronic circuit and the system circuit are implemented with at least one of an ASIC and a FPGA.