# US 2019/0170811 A1 · Semiconductor device structures for burn-in testing and methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0170811 A1 - Document ID: US20190170811A1 - Status: Published application - Kind: A1 - Application number: 16/268,912 - Filed: 2019-02-06 - Published: 2019-06-06 - Earliest claimed: 2017-08-24 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Mark E. Tuttle - Web page: https://patentgrep.com/patent/US20190170811A1 ## CPC - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - G01R 31/2855: {Environmental, reliability or burn-in testing} - G01R 31/2863: {Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04)} - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H10W 20/494: {changeable by the use of an external beam, e.g. laser beam or ion beam} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/0198: {batch processes} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10W 46/601: {for use after dicing} - H10W 70/654: Top-view layouts - H10W 70/655: Fan-out layouts - H10W 70/656: Fan-in layouts - H10W 72/072: {of bump connectors} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9413: {on encapsulations} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/967: {Multiple bond pads having different functions} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad. ## Claims ### Claim 1 A semiconductor device structure, comprising: a substrate; an electrical connection structure extending upwardly from an upper surface of the substrate by a first height; a contact pad electrically disposed on the upper surface of the substrate, the contact pad having a solder-wettable surface with an area configured to support a solder ball having a second height greater than the first height; and a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad. ### Claim 2 (depends on 1) The semiconductor device structure of claim 1, wherein the first height is between about 5 and 30 μm. ### Claim 3 (depends on 1) The semiconductor device structure of claim 1, wherein the second height is greater than about 30 μm. ### Claim 4 (depends on 1) The semiconductor device structure of claim 1, wherein the electrical connection structure is a copper pillar having a diameter of between about 5 and 30 μm. ### Claim 5 (depends on 1) The semiconductor device structure of claim 1, wherein the area of the contact pad is a circle with a diameter of between about 10 and 50 μm. ### Claim 6 (depends on 1) The semiconductor device structure of claim 1, wherein the fuse element is laser-blowable fuse. ### Claim 7 (depends on 6) The semiconductor device structure of claim 6, wherein the laser-blowable fuse is proximate to the electrical connection structure. ### Claim 8 (depends on 1) The semiconductor device structure of claim 1, wherein the fuse element is a blown fuse element. ### Claim 9 A semiconductor device structure, comprising: a substrate; a plurality of electrical connection structures extending upwardly from an upper surface of the substrate by a first height; a plurality of contact pads disposed on the upper surface of the substrate on opposing sides of the plurality of electrical connection structures, each contact pad having a solder-wettable surface with an area configured to support a solder ball having a second height greater than the first height; and a plurality of fuse elements, each fuse element having a first end electrically coupled to a corresponding one of the plurality of electrical connection structures and a second end electrically coupled to a corresponding one of the plurality of contact pads. ### Claim 10 (depends on 9) The semiconductor device structure of claim 9, wherein the first height is between about 5 and 30 μm. ### Claim 11 (depends on 9) The semiconductor device structure of claim 9, wherein the second height is greater than about 30 μm. ### Claim 12 (depends on 9) The semiconductor device structure of claim 9, wherein the plurality of electrical connection structures comprises a plurality of copper pillars each having a diameter of between about 5 and 30 μm. ### Claim 13 (depends on 9) The semiconductor device structure of claim 9, wherein the area of each of the plurality of contact pads is a circle with a diameter of between about 10 and about 50 μm. ### Claim 14 (depends on 9) The semiconductor device structure of claim 9, wherein the plurality of fuse elements comprises a plurality of laser-blowable fuses. ### Claim 15 (depends on 14) The semiconductor device structure of claim 14, wherein each laser-blowable fuses is proximate to the corresponding one of the plurality of electrical connection structures. ### Claim 16 (depends on 9) The semiconductor device structure of claim 9, wherein the plurality of fuse elements comprises a plurality of blown fuse elements. ### Claim 17 A method of testing a semiconductor device including a substrate with a plurality of electrical connection structures extending upwardly from an upper surface of the substrate by a first height, the method comprising: disposing, on a plurality of contact pads electrically coupled to corresponding ones of the plurality of electrical connection structures and disposed on the upper surface of the substrate, a corresponding plurality of solder balls having a second height greater than the first height; connecting, to the plurality of solder balls, a test structure; and electrically testing circuits of the semiconductor device through the test structure. ### Claim 18 (depends on 17) The method according to claim 17, wherein connecting the test structure comprises reflowing the solder balls to form solder junctions between the plurality of contact pads and the test structure. ### Claim 19 (depends on 17) The method according to claim 17, wherein the test structure is supported by the solder junctions a third height above the plurality of electrical connection structures. ### Claim 20 (depends on 17) The method according to claim 17, further comprising reflowing the solder junctions to remove the test structure. ### Claim 21 (depends on 17) The method according to claim 17, further comprising removing the test structure and removing remaining solder from the plurality of contact pads. ### Claim 22 (depends on 17) The method according to claim 17, further comprising electrically decoupling the plurality of contact pads from the plurality of electrical connection structures. ### Claim 23 (depends on 17) The method according to claim 17, wherein first height is between about 5 and 30 μm. ### Claim 24 (depends on 17) The method according to claim 17, wherein the circuits are electrically tested in a burn-in oven.