# US 2019/0170810 A1 · Multi-member test probe structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0170810 A1 - Document ID: US20190170810A1 - Status: Published application - Kind: A1 - Application number: 15/832,650 - Filed: 2017-12-05 - Published: 2019-06-06 - Earliest claimed: 2017-12-05 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Pooya Tadayon; Justin Huttula - Web page: https://patentgrep.com/patent/US20190170810A1 ## CPC - G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)} - G01R 1/06738: {related to tip portion} - G01R 3/00: Apparatus or processes specially adapted for the manufacture {or maintenance} of measuring instruments {, e.g. of probe tips} - G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test. ## Claims ### Claim 1 A testing arrangement for testing Integrated Circuit (IC) interconnects, the testing arrangement comprising: a substrate; and a first interconnect structure comprising: a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end, wherein the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and wherein the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test. ### Claim 2 (depends on 1) The testing arrangement of claim 1, wherein: the first end of the first member and the first end of the second member are attached at a node; and the node is attached to the substrate. ### Claim 3 (depends on 1) The testing arrangement of claim 1, wherein the substrate comprises: a conductive pad, wherein the first end of the first member and the first end of the second member are attached to the conductive pad. ### Claim 4 (depends on 1) The testing arrangement of claim 1, wherein: the second end of the first member and the second end of the second member define a space; and the second interconnect structure of the device under test is to be inserted within the space. ### Claim 5 (depends on 4) The testing arrangement of claim 4, wherein: the first member and the second member are to deflect upon contact with the second interconnect structure of the device under test, such that the space defined by the second end of the first member and the second end of the second member is to increase upon the contact. ### Claim 6 (depends on 1) The testing arrangement of claim 1, wherein: the first member comprises: a first surface at the first end attached to the substrate, a second surface at the second end opposite the first surface, and one or more sidewalls between the first surface and the second surface; and a portion of a sidewall of the one or more sidewalls is to contact the second interconnect structure of the device under test. ### Claim 7 (depends on 1) The testing arrangement of claim 1, wherein the first interconnect structure further comprises: a third member having a first end attached to the substrate and a second end opposite the first end, wherein the second end of the third member is to contact the second interconnect structure of the device under test. ### Claim 8 (depends on 1) The testing arrangement of claim 1, wherein the first member comprises: a core comprising a non-conductive material; and a conductive material on the core. ### Claim 9 (depends on 8) The testing arrangement of claim 8, wherein: the non-conductive material comprises one or more of: a polymer, a negative photoresist material, or SU-8 material; and the conductive material comprises one or more metals. ### Claim 10 (depends on 1) The testing arrangement of claim 1, wherein the first member comprises: one or more metals. ### Claim 11 (depends on 1) The testing arrangement of claim 1, wherein the second end of the first member and the second end of the second member are chamfered to accommodate the second interconnect structure of the device under test. ### Claim 12 (depends on 1) The testing arrangement of claim 1, wherein the testing arrangement further comprises: a third interconnect structure comprising: a third member having a first end attached to the substrate and a second end opposite the first end, and a fourth member having a first end attached to the substrate and a second end opposite the first end, wherein the second end of the third member and the second end of the fourth member are to contact a fourth interconnect structure of the device under test. ### Claim 13 (depends on 1) The testing arrangement of claim 1, wherein: at least a part of the first member is substantially parallel to at least a part of the second member. ### Claim 14 A system comprising: a memory to store instructions; a processor coupled to the memory, the processor to execute the instructions to test a device under test (DUT); and a plurality of probes attached to a substrate, wherein a probe of the plurality of probes comprises a plurality of members, wherein individual members of the plurality of members comprises a first end attached to the substrate and a second end opposite the first end, wherein the second ends of the plurality of members of the probe define a space, and wherein the space defined by the second ends of the plurality of members is to receive an interconnect structure of the DUT. ### Claim 15 (depends on 14) The system of claim 14, wherein: one or more of the plurality of members are to deflect upon contact with the interconnect structure of the DUT, such that the space defined by the second ends of the plurality of members is to increase upon the contact. ### Claim 16 (depends on 14) The system of claim 14, wherein: the plurality of members is arranged in one of a dipod structure, a tripod structure, or a quadpod structure. ### Claim 17 A method comprising: forming a photoresist material over a substrate; and forming a first member and a second member of a probe on the substrate, wherein forming the first member and the second member comprises: forming a mask on the photoresist material, the mask comprising an opening, first exposing a first section of the photoresist material to a light source through the opening, while the substrate is at a first angle with respect to the light source, shifting the mask relative to the substrate, and second exposing a second section of the photoresist material to the light source through the opening, while the substrate is at a second angle with respect to the light source and subsequent to shifting the mask. ### Claim 18 (depends on 17) The method of claim 17, wherein forming the first member and the second member comprises: selectively removing the photoresist layer, without removing the first and second sections of the photoresist material; and depositing metal on the first and second sections of the photoresist material to respectively form the first member and the second member. ### Claim 19 (depends on 18) The method of claim 18, wherein: the first member comprises the first section of the photoresist material and the metal deposited thereon; and the second member comprises the second section of the photoresist material and the metal deposited thereon, wherein the photoresist layer is a negative photoresist material. ### Claim 20 (depends on 17) The method of claim 17, wherein forming the first member and the second member comprises: selectively removing the first and second sections of the photoresist material to respectively form a first opening and a second opening in the photoresist material; depositing metal in the first and second openings to respectively form the first member and the second member; and removing remaining photoresist material, wherein the first member and the second member comprises the metal, wherein the photoresist layer is a positive photoresist material.