# US 2019/0170809 A1 · High speed chip substrate test fixture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0170809 A1 - Document ID: US20190170809A1 - Status: Published application - Kind: A1 - Application number: 15/830,051 - Filed: 2017-12-04 - Published: 2019-06-06 - Earliest claimed: 2017-12-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Lloyd A. Walls; Nam H. Pham; Jason R. Eagle; Nathan L. Dunfee; Pavel Roy Paladhi - Web page: https://patentgrep.com/patent/US20190170809A1 ## CPC - G01R 31/2808: {Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards (probe, multiprobe, probe manipulator or probe fixture G01R1/067)} - G01R 1/0408: {Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets (G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808)} - G01R 1/06722: {Spring-loaded} - G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)} - H05K 1/0243: {Printed circuits associated with mounted high frequency components} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - G01R 1/0466: {concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding} - H05K 1/0268: {for electrical inspection or testing} - H05K 2201/10189: Non-printed connector - H05K 2201/10325: Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support - H05K 2201/10393: Clamping a component by an element or a set of elements - H05K 2203/162: Testing a finished product, e.g. heat cycle testing of solder joints - H10W 44/209: {Vertical interconnections, e.g. vias} - H10W 44/216: {Waveguides, e.g. strip lines} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively. ## Claims ### Claim 1 An apparatus for testing a high-speed signal through a printed circuit board, the apparatus comprising: a multi-layer substrate; one or more transmission lines disposed within the multi-layer substrate; one or more connectors attached to the multi-layer substrate for connecting one or more test cards; a lid, comprising one or more cutouts for the one or more connectors; a clamp for compressing the multi-layer substrate against the pressure place and lid; and one or more high-speed connectors attached to the one or more test cards, respectively. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more transmission lines further comprise an electrical connection between the multi-layer substrate and the test cards. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the one or more test cards further comprise printed circuit board (PCB) cards. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the one or more connectors further comprise a slim-line socket for connecting the PCB cards to the multi-layer substrate. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the lid further comprises an upper layer containing a pillar support and a bottom layer. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the bottom layer comprises a cut out for the pillar support of the upper layer to pass through to the multi-layer substrate. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the one or more high-speed connectors further comprise a sub-miniature version A (SMA) type used for radio frequency (RF) cable connection. ### Claim 8 A multi-layer semiconductor substrate for high speed circuit testing, the multi-layer semiconductor substrate comprising: an upper construct layer; a lower construct layer; one or more intermediate construct layers interposed between the upper construct layer and the lower construct layer; a plurality of high-speed signal traces providing connections to an outer surface of the upper construct and an outer surface of the lower construct and passing through the one or more intermediate construct layers; one or more ground-return-vias or signal return vias connecting the upper construct layer and the adjacent intermediate construct layer; and one or more closed loop signal traces etched on the upper construct layer for minimizing electrical noise. ### Claim 9 (depends on 8) The multi-layer semiconductor substrate of claim 8, wherein the upper construct layer further comprises a grounding layer containing one or more grounding traces. ### Claim 10 (depends on 8) The multi-layer semiconductor substrate of claim 8, wherein the lower construct layer further comprises a grounding layer containing one or more grounding traces. ### Claim 11 (depends on 8) The multi-layer semiconductor substrate of claim 8, wherein the plurality of high-speed signal traces further comprise one or more electrical connections between a slim-line socket and a system board. ### Claim 12 (depends on 9) The multi-layer semiconductor substrate of claim 9, wherein the one or more ground-return-vias further comprises a via electrically connecting the grounding traces of the upper construct layer and the adjacent intermediate construct layer. ### Claim 13 (depends on 11) The multi-layer semiconductor substrate of claim 11, wherein the one or more closed loop signal traces further comprise an electrical pathway connecting pairs of pins associated with the slim-line socket. ### Claim 14 A system of for testing a high speed signal through a printer circuit board, the system comprising: a substrate; a transmission line disposed within the substrate; one or more connectors attached to the substrate for connecting one or more test cards; a lid, comprising one or more cutouts for the one or more connectors; a clamp for compressing the substrate against the lid; one or more high-speed connectors attached to the one or more test cards, respectively; and a signal analyzer connected to the one or more high speed connectors. ### Claim 15 (depends on 14) The system of claim 14, wherein the one or more transmission lines comprises an electrical connection between the substrate and the test cards. ### Claim 16 (depends on 14) The system of claim 14, wherein the one or more test cards comprises printed circuit boards (PCB) cards. ### Claim 17 (depends on 14) The system of claim 14, wherein the one or more connectors comprises a slim-line socket for connection the PCB cards to the substrate. ### Claim 18 (depends on 14) The system of claim 14, wherein the lid further comprises an upper layer containing a pillar support and a bottom layer. ### Claim 19 (depends on 18) The system of claim 18, wherein the bottom layer comprises a cut out for the pillar support of the upper layer to pass through to the multi-layer substrate. ### Claim 20 (depends on 14) The system of claim 14, wherein the one or more high-speed connectors further comprise a sub-miniature version A (SMA) type used for radio frequency (RF) cable connection.