# US 2019/0170682 A1 · Apparatus based on a nanowire cross for measuring small potentials of a sample, method for producing the apparatus, and use of the apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0170682 A1 - Document ID: US20190170682A1 - Status: Published application - Kind: A1 - Application number: 16/324,157 - Filed: 2017-09-06 - Published: 2019-06-06 - Earliest claimed: 2016-09-08 - Assignees: Forschungszentrum Juelich GmbH - Applicants: Forschungszentrum Juelich GmbH - Inventors: Svetlana VITUSEVICH; Ihor ZADOROZHNYI - Web page: https://patentgrep.com/patent/US20190170682A1 ## CPC - G01N 27/4146: {involving nanosized elements, e.g. nanotubes, nanowires} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/123: {comprising junctions} - H10D 99/00: Subject matter not provided for in other groups of this subclass - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An apparatus for measuring electrical potentials of a liquid sample includes at least one field effect transistor having a source, a drain, and a gate, a substrate, and at least two intersecting nanowires of semiconductive material arranged on the substrate, each having a source and drain contact as a field effect transistor and a voltage applicator configured to apply a voltage between the respective source and drain contact. The cross section of the two nanowires has a shape of a triangle or a trapezium. A voltage applicator configured to apply a voltage to the substrate are arranged on the substrate. The nanowires are electrically insulated at least against the sample by a dielectric layer along their surface having a layer thickness between 5 and 40 nm, and at least one impurity is arranged in the dielectric layer as a bearing point which is capable of capturing charge carriers. ## Claims ### Claim at position 1 1: An apparatus for measuring electrical potentials of a liquid sample, the apparatus comprising: at least one field effect transistor having a source, a drain, and a gate; a substrate; and at least two intersecting nanowires of semiconductive material arranged on the substrate, each having a source and drain contact as a field effect transistor and a voltage applicator configured to apply a voltage between the respective source and drain contact, wherein a cross section of the two nanowires has a shape of a triangle or a trapezium, wherein a voltage applicator configured to apply a voltage to the substrate is arranged on the substrate, wherein the nanowires are electrically insulated at least against the sample by a dielectric layer along their surface having a layer thickness between 5 and 40 nm, and wherein at least one impurity is arranged in the dielectric layer as a bearing point which is capable of capturing charge carriers from at least one of the two nanowires and, conversely, emitting the charge carriers to the at least one of the two nanowires. ### Claim 2 (canceled) ### Claim at position 3 (depends on 1) 3: The apparatus according to claim 1, wherein on the dielectric layer, a platelet of metal is disposed on each nanowire on each side of the respective nanowire around the common intersection region of the nanowires, wherein opposing platelets each form an antenna. ### Claim 4 (canceled) ### Claim at position 5 (depends on 1) 5: The apparatus according to claim 1, wherein at least one section of at least one nanowire has a different width and/or height than the rest of this nanowire. ### Claim at position 6 6: A method for producing an apparatus for measuring electrical potentials of a liquid sample, the apparatus comprising at least one field effect transistor with source, drain and gate, the method comprising: arranging a semiconductive layer on a substrate; arranging, using a mask with a cross-shaped structure, at least two intersecting semiconductive nanowires in the semiconductor layer as a field effect transistor in an anisotropic etching process, wherein a cross section of the two nanowires has the shape of a triangle or trapezium, wherein source and drain contacts are arranged on each nanowire, wherein a voltage applicator configured to apply a voltage to the substrate is arranged on the substrate, wherein, on the surface of the nanowires, a dielectric layer having a layer thickness of between 5 and 40 nm is arranged, wherein in this dielectric layer, by way of electromagnetic radiation, at least one impurity is selectively produced as a bearing point which is capable of capturing charge carriers from at least one of the two nanowires and, conversely, of emitting the charge carriers to the at least one of the two nanowires. ### Claim at position 7 (depends on 6) 7: The method according to claim 6, wherein an anisotropic etching process comprises at least two etching steps using a respective mask in each etching step. ### Claim 8 (canceled) ### Claim at position 9 (depends on 6) 9: The method according to claim 6, characterized by the steps: a) at least one semiconducting layer is arranged on a substrate, b) a pattern of a virtual or physical mask is provided, said pattern comprising two axially symmetrical structures along their longitudinal axis which intersect and each have at least one overall or sectional rectangular or square shape, c) an etchant, which anisotropically etches the material of the semiconducting layer, is applied to at least one edge of a surface on the semiconducting layer which is congruent with the total surface area of the pattern, d) step c) is repeated for opposite edges of the border of the surface mentioned in step c) until at least two intersecting nanowires of triangular or trapezoidal cross-section are arranged along the longitudinal axes of the surface with a source and/or drain elevation arranged at each end of the nanowires, e) a dielectric layer is arranged along the surface of the nanowires, f) at least one bearing point is arranged in the dielectric layer along the surface of the wires, g) the elevations intended for drain and source and the substrate are electro-conductively connected with means for applying a voltage. ### Claim at position 10 (depends on 9) 10: The method according to claim 9, wherein the arrangement of the etchant according to step c) is carried out in the following sub-steps: i) the etchant is arranged at least at a first edge of the surface mentioned in step c), wherein no etchant is arranged at least between the longitudinal axis of this surface which is parallel to the first edge and a second edge opposite the first edge, ii) the etchant is removed and subsequently arranged at least at the second edge, wherein at least between the longitudinal axis from step i) and the first edge no etchant is arranged, iii) the etching process in steps i) and ii) is carried out according to step d). ### Claim at position 11 (depends on 9) 11: The method according to claim 9, wherein the arrangement of the etchant in step c) is carried out in the following steps: i) at least one further layer is arranged on the semiconducting layer, said layer comprising a material which can be removed after irradiation with electron beams and/or light beams and/or ion beams, ii) a mask is provided which has at least one surface that matches the total surface area of the pattern, iii) the further layer is irradiated with electron beams and/or light and/or ion beams through the mask, iv) the regions of the further layer, which have been irradiated through the mask, are removed, v) the etchant is arranged at least on the surface of the semiconducting layer on the surface, on which the removed regions of the further layer were arranged, vi) the process is continued according to step d), wherein the etchant is arranged at the edges of the surface of step c) in each case after using a mask according to step ii). ### Claim at position 12 (depends on 11) 12: The method according to claim 11, wherein in each case, the provided mask comprises the total surface area of the pattern and two further surface areas which are arranged in diametrically opposed quadrants which are delimited by the two longitudinal axes of the total surface area of the pattern and together with the partial surface of the pattern form a square or rectangle in the respective quadrant. ### Claim at position 13 (depends on 11) 13: The method according to claim 11, wherein in each case, the provided mask comprises the total surface area of the pattern and three further surface areas which are each arranged in a quadrant, which are delimited by the two longitudinal axes of the total surface area of the pattern and together with the partial surface of the pattern form a square or rectangle in the respective quadrant. ### Claim at position 14 (depends on 6) 14: The method according to claim 6, wherein platelets made of metal, in particular gold platelets, are vapor-deposited onto the dielectric layer on the surface of each nanowire. ### Claim at position 15 (depends on 6) 15: The method according to claim 6, wherein at least one of the rectangular structures in the pattern of the mask used has different widths in different sections. ### Claim at position 16 (depends on 1) 16: A method for determining the pH of the liquid sample using the apparatus according to claim 1, wherein from the time constants τc or the time constant τe, the pH value of the sample is determined, wherein the time constant τc is the time interval, in which the drain current assumes its maximum value, and the time constant τe is the time interval, in which the drain current assumes its minimum value.