Method for puf generation using variations in transistor threshold voltage and subthreshold leakage current

A method to configure a physical unclonable function (PUF) generator for generating a PUF signature, the method comprising:

• coupling a plurality of PUF cells to a plurality of DFF circuits, and to a population counter and further to an evaluation logical circuit, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor;
• charging a plurality of dynamic nodes in the plurality of PUF cells to a plurality of first voltages through each of the plurality of first MOS transistors;
• discharging the plurality of dynamic nodes to a plurality of second voltages through each of the plurality of second MOS transistors;
• monitoring each of the plurality of second voltages using corresponding dynamic flip-flop (DFF) circuits;
• flipping logical states of the plurality of PUF cells from a first logical state to a second logical state when the second voltage becomes smaller than a third voltage;
• and
• generating a PUF signature when a number of PUF cells having flipped logical states are more than half of a total number of PUF cells.

A physical unclonable function (PUF) generator for generating a PUF signature, the PUF generator comprising:

• A plurality of PUF cells, wherein each of the plurality of PUF cells comprises five MOS transistors, wherein a first and a second MOS transistors are configured to charge and discharge a first dynamic node, a third and a fourth MOS transistors are configured to charge a second dynamic node, and a fifth MOS transistor is configured to discharge the second dynamic node so as to reset the second dynamic node.
• a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively, wherein the plurality of DFF circuits each is configured to monitoring a voltage level on the dynamic node on each of the plurality of PUF cells;
• a population count circuit coupled to the plurality of DFF circuits, wherein the population count circuit is configured to determine a first number of PUF cells having flipped logical states;
• and
• an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of DFF circuits, wherein the evaluation logic circuit is configured to compare the first number with half of a total number of PUF cells.