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US 2019/0165919 A1Published application
Interface circuit and information processing system
AssigneeSony Corporation
InventorsKAZUAKI TOBA, GEN ICHIMURA
Life of this patent
Estimating the term…
Abstract
A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.
Claims21
An interface circuit comprising:
- a first transmitting unit which transmits a first signal including a clock component to an external device through a transmission path as a differential signal;
- a second transmitting unit which superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device;
- and
- a state notifying unit which communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.
1 more element
An interface circuit comprising:
- a first transmitting unit which transmits a first signal including a clock component to an external device through a transmission path as a differential signal;
- a second transmitting unit which superimposes a second signal for decrypting the first signal on the transmission path as an in-phase signal to transmit to the external device;
- and
- a state notifying unit which communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.
1 more element
An interface circuit comprising:
- a first transmitting unit which transmits a first signal to an external device through a transmission path as a differential signal;
- a second transmitting unit which superimposes a second signal including a clock component of the first signal on the transmission path as an in-phase signal to transmit to the external device;
- and
- a state notifying unit which communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.
1 more element
An interface circuit comprising:
- a first receiving unit which extracts a first signal including a clock component from a differential signal received from an external device through a transmission path;
- a second receiving unit which extracts a second signal including a clock component from an in-phase signal received from the external device through the transmission path;
- and
- a state receiving unit which communicates with the external device through a pair of differential transmission paths included in the transmission path and is notified by the external device of a connection state by a DC bias potential of at least one of the pair of differential transmission paths.
1 more element
An interface circuit comprising:
- a first receiving unit which extracts a first signal including a clock component from a differential signal received from an external device through a transmission path;
- a second receiving unit which extracts a second signal for decrypting the first signal from an in-phase signal received from the external device through the transmission path;
- and
- a state receiving unit which communicates with the external device through a pair of differential transmission paths included in the transmission path and is notified by the external device of a connection state by a DC bias potential of at least one of the pair of differential transmission paths.
1 more element
An interface circuit comprising:
- a first receiving unit which extracts a first signal from a differential signal received from an external device through a transmission path;
- a second receiving unit which extracts a second signal including a clock component of the first signal from an in-phase signal received from the external device through the transmission path;
- and
- a state receiving unit which communicates with the external device through a pair of differential transmission paths included in the transmission path and is notified by the external device of a connection state by a DC bias potential of at least one of the pair of differential transmission paths.
1 more element
An information processing system obtained by connecting a first interface circuit and a second interface circuit to each other through a transmission path, wherein
- the first interface circuit is provided with a first transmitting unit which transmits a first signal including a clock component to the second interface circuit through the transmission path as a differential signal, a second transmitting unit which superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the second interface circuit, and a state notifying unit which communicates with the second interface circuit through a pair of differential transmission paths included in the transmission path and notifies the second interface circuit of a connection state of the first interface circuit by a DC bias potential of at least one of the pair of differential transmission paths, and
- the second interface circuit is provided with a first receiving unit which extracts the first signal including the clock component from the differential signal received from the first interface circuit through the transmission path, a second receiving unit which extracts the second signal including the clock component from the in-phase signal received from the first interface circuit through the transmission path, and a state receiving unit which communicates with the first interface circuit through the pair of differential transmission paths included in the transmission path and is notified by the first interface circuit of the connection state by the DC bias potential of at least one of the pair of differential transmission paths.
Dependencies are inferred from the claim text.