# US 2019/0165828 A1 · Systems and methods for ultra wideband impulse radio transmitters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0165828 A1 - Document ID: US20190165828A1 - Status: Published application - Kind: A1 - Application number: 16/261,797 - Filed: 2019-01-30 - Published: 2019-05-30 - Earliest claimed: 2015-06-01 - Assignees: Transfert Plus, Societe en Commandite - Applicants: Transfert Plus Societe En Commandite - Inventors: FREDERIC NABKI; DOMINIC DESLANDES; MOHAMMAD TAHERZADEH-SANI; MICHIEL SOER - Web page: https://patentgrep.com/patent/US20190165828A1 ## CPC - H04B 1/717: Pulse-related aspects - H04B 1/1615: {Switching on; Switching off, e.g. remotely (battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34)} - H04B 1/385: {Transceivers carried on the body, e.g. in helmets} - H04B 1/7163: using impulse radio - H04B 1/7183: Synchronisation - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 5/0044: {Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH} - H04L 7/00: Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} - H04L 7/0091: {Transmitter details} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H04L 25/00: Baseband systems - H04L 25/03834: {using pulse shaping} - H04L 25/4902: {Pulse width modulation; Pulse position modulation} - H04L 27/22: Demodulator circuits; Receiver circuits - H04L 27/2647: {Arrangements specific to the receiver only (equalisation H04L27/01)} - Y02D 30/70: in wireless communication networks - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications. ## Claims ### Claim 1 A transmitter for an impulse radio comprising: a radio frequency (RF) signal generator for transmitting data, the RF signal generator receiving a data signal to be transmitted and generating a transmission signal for coupling to an antenna. ### Claim 2 (depends on 1) The transmitter according to claim 1, wherein each bit of the data signal to be transmitted is converted into a predetermined portion of the transmission signal; the predetermined portion of the transmission signal comprising a plurality N pulses generated by the RF signal generator wherein each pulse of the N pulses is at a predetermined frequency of a plurality M frequencies, has a predetermined amplitude, and has a predetermined pulse length. ### Claim 3 (depends on 1) The transmitter according to claim 1, wherein the transmitter circuit comprises: a pulse pattern block for receiving a clock signal storing a configuration of a plurality of pulses comprising a symbol pulse bundle employed to represent a current symbol of the data signal within the transmission signal; a clock signal generator for receiving the clock signal and generating a plurality of phased clocks, each phased clock of the plurality of phased clocks having a predetermined phase relationship to the other phased clocks of the plurality of phased clocks and representing the start of a pulse in a symbol pulse bundle; a multiplexer for receiving the plurality of phased clocks from the clock signal generator and selecting a configuration for the current pulse of the symbol pulse bundle from the pulse pattern block; a pulse generator coupled to the multiplexer for generating an enable pulse with a pulse width set by the configuration for the current pulse of the symbol pulse bundle employed to enable a digitally controlled oscillator; the digitally controlled oscillator coupled to the multiplexer generating pulses of predetermined shape with a frequency set by the configuration for the current pulse of the symbol pulse bundle when enabled by the enable pulse from the pulse generator. ### Claim 4 (depends on 3) The transmitter according to claim 3, further comprising an amplifier for receiving the output of the digitally controlled oscillator and amplifying it when enabled by the enable pulse from the pulse generator. ### Claim 5 (depends on 3) The transmitter according to claim 3, wherein the configuration of the plurality of pulses comprising the symbol pulse bundle employed to represent the current symbol of the data signal comprises a plurality N pulses; wherein each pulse of the N pulses is at a predetermined frequency of a plurality M frequencies, has a predetermined amplitude, and has a predetermined pulse length. ### Claim 6 (depends on 3) The transmitter according to claim 3, wherein the pulse pattern block is dynamically updated during generation of the transmission signal. ### Claim 7 (depends on 6) The transmitter according to claim 6, wherein the dynamic updating of the pulse pattern block is based upon one or more of network environment data received by the transmitter, a predetermined sequence, a date of transmission, the time of transmission, a geographic location of the transmitter, and a regulatory mask. ### Claim 8 (depends on 6) The transmitter according to claim 6, wherein the dynamic updating of the pulse pattern block is based upon a measure of a signal-to-noise ratio of wireless signals received by a receiver ### Claim 9 (depends on 1) The transmitter according to claim 1, wherein the RF signal generator comprises an amplifier; the amplifier receives pulses to be amplified and a shaping signal applied to a ground node; the amplifier amplifies and shapes the received pulse in dependence upon the shaping signal. ### Claim 10 (depends on 9) The amplifier according to claim 9, wherein the shaping signal results in the amplified output pulses having a Gaussian profile such that sidelobes in the pulse spectrum are reduced. ### Claim 11 (depends on 9) The transmitter according to claim 9, wherein the amplifier comprises a pair of coupled transistors having their sources coupled to the ground node and their drains connected to a power supply; first and second clock signals are applied to the gates of each transistor of the pair of coupled transistors; a drain of a third transistor is coupled to the ground node and to ground by a capacitor; the source of the third transistor is coupled to ground; the shaping signal comprises a pulse applied to the gate of the third transistor which defines the duration of an output pulse from the amplifier; and the third transistor and capacitor shape the pulse of the shaping signal such that the amplifier generates an amplified pulse with a Gaussian profile. ### Claim 12 (depends on 1) The transmitter according to claim 1, wherein the RF signal generator comprises a fully differential-ring digitally controlled oscillator (FDR-DCO), a pulser circuit, and an amplifier; the FDR-DCO provides first and second clock signals to the amplifier and is coupled to output of the pulser; the frequency of the FDR-DCO is established by first and second capacitor banks each disposed between a pair of fully-differential inverters in a chain of fully-differential inverters, each of the first and second capacitor banks comprising a pair of capacitors with each capacitor of the pair of capacitors is disposed between an output of a preceding fully-differential inverter and the input of a next fully-differential inverter and coupled to ground; the outputs of the last fully-differential inverter in the chain of fully-differential inverters provides the first and second clock signals and are fed back to the first fully-differential inverter in the chain of fully-differential inverters. ### Claim 13 (depends on 12) The transmitter according to claim 12, wherein the output of the pulser circuit is coupled to a first input of the first fully-differential inverter in the chain of fully-differential inverters within the FDR-DCO via a first switch and coupled to a second input of the first fully-differential inverter in the chain of fully-differential inverters within the FDR-DCO via an inverter and a second switch; the outputs of the last fully-differential inverter in the chain of fully-differential inverters are fed back to the first fully-differential inverter in the chain of fully-differential inverters via third and fourth switches; the inverter, the first switch, and the second switch pre-charge the FDR-DCO and control the polarity of pulses generated by the FDR-DCO; in a first configurate the FDR-DCO is configured to generate a pulse by opening the first and second switches and closing the third and fourth switches; and in a second configuration the FDR-DCO is in a low power sleep state by closing the first and second switches and opening the third and fourth switches. ### Claim 14 (depends on 12) The transmitter according to claim 12, wherein each capacitor within the pair of capacitors have the same capacitance values; and each capacitor within the pair of capacitors forming each of the first and second capacitor banks comprises a programmable capacitor bank having N bits of programmability. ### Claim 15 (depends on 1) The transmitter according to claim 1, wherein the RF signal generator comprises an amplifier, a digitally controlled oscillator (DCO) and a pulser circuit; the pulser circuit for generating pulse signals coupled to the amplifier and DCO; and the pulser circuit generates a pulse in response to a rising edge of a data signal coupled to the input of the pulser circuit; and the pulse width of the pulse is established in dependence upon a setting of a variable delay within the pulser circuit which is digitally programmed. ### Claim 16 (depends on 1) The transmitter according to claim 1, wherein the RF signal generator comprises a clock generation circuit comprising: a low frequency oscillator generating a sinusoidal oscillator signal at a first predetermined frequency; a converter circuit for converting the sinusoidal oscillator signal at the first predetermined frequency to a square wave clock at the first predetermined frequency; and a phase locked loop for generating an output clock signal at a second predetermined frequency. ### Claim 17 (depends on 16) The transmitter according to claim 16, wherein the low frequency oscillator is a 32 kHz oscillator; the clock generation circuit generates a base clock equal to the symbol frequency of data to be transmitted; and the base clock signal is 20 MHz. ### Claim 18 (depends on 1) The transmitter according to claim 1, wherein the RF signal generator comprises a clock generation circuit employing a phase locked loop (PLL) in conjunction with a low frequency oscillator and a pulse generator employing a delay locked loop (DLL); the transmitter transmits data according to a protocol comprising a plurality of frames; at data rates below a predetermined threshold the DLL and PLL are power cycled to a sleep mode between transmission of each frame of the plurality of frames whilst the low frequency oscillator remains active; and at data rates above the predetermined threshold the DLL and PLL remain on between transmission of each frame of the plurality of frames whilst the low frequency oscillator remains active. ### Claim 19 (depends on 1) The transmitter according to claim 1, further comprising a control circuit for controlling operation of the transmitter; wherein the transmitter transmits data according to a protocol comprising a plurality of frames each of fixed size and symbol rate; and the control circuit can configure the transmitter to support a plurality of effective data rates by adjusting the length of a sleep period between each frame of the plurality of frames.